- 26 Oct, 2009 11 commits
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Robert Noland authored
Fix the main loop to search all buffers before sleeping. Remove dead code Signed-off-by:
Robert Noland <rnoland@2hip.net> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Try to enable msi on chips that support it. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
Spread spectrum is a periodic disturbance added to the feedback divider to change the pixel clock periodically to reduce interference. Only enabled on LVDS. v2: add support for r4xx and fix DCE 3 Signed-off-by:
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Alex Deucher authored
The *_HIGH regs are reversed. The secondary ones are in the primary block and vice versa. We currently only use a 32 bit internal address, so these are 0 for now. Signed-off-by:
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Robert Noland authored
This patch only changes this is the swap path, where it doesn't loop. Signed-off-by:
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Robert Noland authored
- Reduce the chance of error and avoid a bit of overhead. - Use switch to assign color and format Signed-off-by:
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Mathias Fröhlich authored
Where supported use ulMinPixelClockPLL_Output rather than usMinPixelClockPLL_Output for pll_out_min. This seems to improve pll selection on some boards. Signed-off-by:
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Alex Deucher authored
doesn't have a tv-out port Signed-off-by:
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Alex Deucher authored
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Mathias Fröhlich authored
The problem boils down to the order when the bit11 of the texture size is or'ed to the original width. In the end each mipmap level has the same width or height because of that 11 bit is ored to the scaled down lod with and thus blows up the size again to the full size or more due to the power of two rounding afterwards. The attached patch changes this order so that the texture sizes are computed correct. Also the on error the yet missing inputs to the size computation are printed which helped me to find out where it really breaks. Signed-off-by:
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Dave Airlie authored
This sets the fbcon to use TRUECOLOR by default, it then only modifies the pseudo palette for fbcon, and only touches the real palette when in 8-bit pseudo color mode. Signed-off-by:
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- 16 Oct, 2009 2 commits
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Alex Deucher authored
Original radeon didn't have a connector table in the bios. Check for the CRT table and if we have one, add a VGA connector. Signed-off-by:
Dave Airlie <airlied@linux.ie>
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Alex Deucher authored
Need to check the return type for the quirk function to decide whether we add the connectors and encoders. Signed-off-by:
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- 15 Oct, 2009 7 commits
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Zhao Yakui authored
Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by:
Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
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Matt Turner authored
Signed-off-by:
Matt Turner <mattst88@gmail.com> Signed-off-by:
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Alex Deucher authored
fixes fdo bug 24496 Signed-off-by:
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Alex Deucher authored
D1MODE_INTERLEAVE_EN was getting set in some cases in the encoder quirks function due to the changes in 5a9bcaccSigned-off-by:
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Alex Deucher authored
Based partly on a patch from Christian Koenig <deathsimple@vodafone.de> - fix several memory leaks in radeon_connector->edid handling - store edid in radeon_connector->edid in detect() or get_modes() - switch hdmi detect code to use radeon_connector->edid - add support for oem boards multiple connectors that share a ddc line. - short circuit lvds_detect() if have a stored edid Signed-off-by:
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Alex Deucher authored
- crtc 0 routing was wrong - need to clear various timing bits in FP_GEN_CNTL - need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1 Signed-off-by:
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Alex Deucher authored
radeon_encoder->active_device defines the active routing between the encoder and connector. The encoder fixup and dpms functions need to know the active_device to function properly. Setting active_device in the prepare hook was too late in some cases. Signed-off-by:
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- 12 Oct, 2009 12 commits
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Alex Deucher authored
drm modes are objects with indentifiers. Make sure to preserve the mode id when copying mode params. Signed-off-by:
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Dave Airlie authored
With the adjust table introduction, we need to fill out index before getting the table version. Signed-off-by: -
Dave Airlie authored
This reverts commit 49c458e5. It seems to have some side effects in the non-kms cases. Signed-off-by:
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Alex Deucher authored
In case the system has bad native mode info but valid edid. Signed-off-by:
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Alex Deucher authored
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by:
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Alex Deucher authored
- clean up tv timing handling - unify SetCRTC_Timing and SetCRTC_UsingDTDTiming Signed-off-by:
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Alex Deucher authored
DCE3+ has an AdjustDisplayPll that will adjust the pixel clock accordingly based on the encoder/transmitter to handle special hw requirements. Signed-off-by:
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Alex Deucher authored
Based on recommendation from bios docs. Signed-off-by:
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Alex Deucher authored
If the panel data is bogus this can lead to problems later when the hardware trys to set the mode. If the data is invalid, report LVDS as disconnected. Should fix fdo bug 24247. Signed-off-by:
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Michel Dänzer authored
While investigating the cause of CRTC FIFO underruns, I noticed that when converting the memory bandwidth calculation from the userspace X driver code, an instance of '8.0' was apparently accidentally converted to '80'. Signed-off-by:
Michel Dänzer <daenzer@vmware.com> Signed-off-by:
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Michel Dänzer authored
The hook may change the number of bytes per pixel being scanned out, which affects the CRTC memory bandwidth requirements. E.g. booting in 8bpp and then running X in 32bpp would result in the bandwidth requirements being underestimated for the latter and consequently in CRTC FIFO underruns causing visible artifacts with 3D intensive workloads. ATOM changes only compile-tested. Signed-off-by:
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Dave Airlie authored
The fb binding might be happening in a subsequent crtc setup call. gets rid of some lut issues. Signed-off-by:
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- 08 Oct, 2009 1 commit
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Dave Airlie authored
Both r100/r600 had this wrong, use the macro to extract the register to relocate. Signed-off-by:
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- 07 Oct, 2009 6 commits
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Robert Noland authored
There is no need to assign vb before you know that space is available. [agd5f: adapted for kernel tree.] Signed-off-by:
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Dave Airlie authored
This is just a cleanup of the list macro usage. Signed-off-by: -
Jerome Glisse authored
For AGP to work unmapped access must cover VRAM & AGP as AGP is treated like VRAM by the GPU (ie physical address). This patch properly setup the virtual memory system aperture to cover AGP if AGP is enabled. It seems that there is memory corruption after resume when using AGP (RV770 seems unaffected thought). Version 2 just fix merge issue with updated AGP fallback patch. Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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Jerome Glisse authored
When GPU acceleration is not working with AGP try to fallback to non AGP GART (either PCI or PCIE GART). This should make KMS failure on AGP less painfull. We still need to find out what is wrong when AGP fails but at least user have a lot of more chances to get a working configuration with acceleration. This patch also cleanup R600/RV770 fallback path so they use same code as others asics. Version 2 factorize agp disabling logic to avoid code duplication and bugs. Signed-off-by:
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Jerome Glisse authored
Bad generated header file leaded to use wrong register to check IRQ status and acknowledge them. Fix the header and use proper registers. Signed-off-by:
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Roel Kluin authored
Duplicate bits set Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
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- 06 Oct, 2009 1 commit
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Dave Airlie authored
the global refcount wasn't being increased after the first reference. this caused an oops on unload on a multi-gpu card. Signed-off-by:
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