- 14 Feb, 2017 1 commit
-
-
Thomas Petazzoni authored
This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
-
- 10 Feb, 2017 2 commits
-
-
Chris Packham authored
The initial implementation in commit e120c17a ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
-
Baoyou Xie authored
The i2s related clock support is missing from the existing zx296718 clock driver. This patch adds it, so that the upstream ZX I2S driver can work out. Signed-off-by:
Baoyou Xie <baoyou.xie@linaro.org> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
-
- 06 Feb, 2017 3 commits
-
-
Wei Yongjun authored
PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong error code will be returned. Fixes: 783ab76a ("clk: sunxi-ng: Add A80 Display Engine CCU") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
-
Arnd Bergmann authored
We get a link error when CCU_MULT is not set with the newly added driver: drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.17+0x4): undefined reference to `ccu_mult_ops' drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.5+0x4): undefined reference to `ccu_mult_ops' Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
-
Stephen Boyd authored
This kzalloc() could fail. Let's bail out with -ENOMEM here instead of NULL dereferencing. That silences static checkers. We should also cleanup on the error path even though this function returning an error probably means the system won't boot. Cc: Chen-Yu Tsai <wens@csie.org> Acked-by:
-
- 03 Feb, 2017 5 commits
-
-
Thierry Reding authored
This driver uses the services provided by the BPMP firmware driver to implement a clock driver based on the MRQ_CLK request. This part of the BPMP ABI provides a means to enumerate and control clocks and should allow the driver to work on any chip that supports this ABI. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
-
Stephen Boyd authored
Merge tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: "Non-critical fix for the pclk_edp divider on rk3399, one new clock-id and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees." * tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3288: make all niu clocks critical clk: rockchip: use rk3288 vip_out clock ids clk: rockchip: add rk3288 vip_out clock id clk: rockchip: fix the incorrect pclk_edp div width for RK3399
-
Masahiro Yamada authored
Add clock for the Cadence eMMC controller on LD11/LD20. For the other SoCs, the clock for the eMMC controller is included in the MIO/SD control block. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
-
Masahiro Yamada authored
Add clock line for the Denali NAND controller. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock updates from Maxime Ripard: - Support for one new SoC, the V3s - Conversion of two old SoCs to the new framework, the old sun5i family and the A80 - A bunch of fixes * tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU clk: sunxi-ng: Call divider_round_rate if we only have a single parent ARM: gr8: Convert to CCU ARM: sun5i: Convert to CCU clk: sunxi-ng: Add sun5i CCU driver clk: sunxi-ng: Implement global pre-divider clk: sunxi-ng: Implement multiplier maximum clk: sunxi-ng: mult: Fix minimum in round rate clk: sunxi-ng: Implement factors offsets clk: sunxi-ng: multiplier: Add fractional support clk: sunxi-ng: add support for V3s CCU dt-bindings: add device binding for the CCU of Allwinner V3s ...
-
- 30 Jan, 2017 8 commits
-
-
Chen-Yu Tsai authored
Now that we have a full clock driver for sun9i, switch to it. Signed-off-by:
-
Chen-Yu Tsai authored
With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by:
-
Chen-Yu Tsai authored
Add support for the USB clock controls found on the A80. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Chen-Yu Tsai authored
Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by:
-
Chen-Yu Tsai authored
On the Allwinner A80 SoC, the PLL lock status indicators are grouped together in a separate register, as opposed to being scattered in each PLL's configuration register. Add a flag to support this. Signed-off-by:
-
Chen-Yu Tsai authored
If the CLK_SET_RATE_PARENT flag is set, we want to try getting the closest parent rate. Signed-off-by:
-
Chen-Yu Tsai authored
This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the mux determine_rate helper, based on examples from clk-composite and clk-mux. Signed-off-by:
-
Chen-Yu Tsai authored
The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() to adjust the parent_rate to account for pre-dividers, but then passed the pristine parent clock rate from clk_hw_get_rate() to the round() callback, thereby ignoring the pre-divider adjustment. In addition, it was saving the adjusted parent rate back into struct clk_rate_request. This patch fixes this by saving the pristine parent clock rate, and adding a copy that is adjusted and passed to the round() callback. The pristine copy, if it is the best solution, would be saved back to struct clk_rate_request. Signed-off-by:
-
- 27 Jan, 2017 21 commits
-
-
Jeremy McNicoll authored
Add missing clock branch to enable onboard storage for msm899(2/4). Signed-off-by:
Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by:
-
Jeremy McNicoll authored
AHB clock branch is needed in order to enable SDHCI on msm899(2/4). Signed-off-by:
-
git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Use CLK_IS_CRITICAL to handle critical clocks, - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1, - Add IIC-DVFS clocks for R-Car H3 and M3-W, - Minor cleanups. * tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add IIC-DVFS clock clk: renesas: r8a7795: Add IIC-DVFS clock clk: renesas: cpg-mssr: Add support for reset control clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock clk: renesas: cpg-mssr: Document suitability for RZ/G1 dt-bindings: clock: renesas: cpg-mssr: Document reset control support clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff clk: renesas: mstp: Make INTC-SYS a critical clock clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
-
Chris Packham authored
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by:
-
Martin Kaiser authored
These functions are referencing s3c...._clk_regs[], which are marked as __initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this produces warnings like WARNING: vmlinux.o(.text+0x198350): Section mismatch in reference from the function s3c2410_clk_sleep_init() to the (unknown reference) .init.data:(unknown) Mark the s3c...._clk_sleep_init() functions as __init in order to fix this. Fixes: ca2e90ac ("clk: samsung: add clock controller driver for s3c2412") Signed-off-by:
Martin Kaiser <martin@kaiser.cx> Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
-
Marek Szyprowski authored
Some PLLs might be disabled by default after turning off and then on a power domain which they belongs to. To avoid configuring a disabled PLL, add proper code for handling PLL enable/disable. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
-
Marek Szyprowski authored
This patch fixes simple typos in Exynos5433 clocks driver. The SoC name was referred a few times as '5443' instead of '5433'. Signed-off-by:
-
Marek Szyprowski authored
Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clock-*' properties, parameters for those two additional rates are needed. Signed-off-by:
-
Marek Szyprowski authored
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by:
-
Maxime Ripard authored
In order to achieve all the rates asked by the GPU, we might need to change the parent frequency. Signed-off-by:
-
Maxime Ripard authored
The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does. If we have a single parent, call divider_round_rate. Signed-off-by:
-
Khiem Nguyen authored
This patch adds DVFS clock for R8A7796 SoC. Signed-off-by:
Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by:
Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
-
Keita Kobayashi authored
This patch adds DVFS clock for R8A7795 SoC. Signed-off-by:
Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by:
Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by:
-
Geert Uytterhoeven authored
Add optional support for the Reset Control feature of the Renesas Clock Pulse Generator / Module Standby and Software Reset module on R-Car Gen2, R-Car Gen3, and RZ/G1 SoCs. This allows to reset SoC devices using the Reset Controller API. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
-
Geert Uytterhoeven authored
The spinlock is used to protect Read-Modify-Write register accesses, which won't be limited to SMSTPCR register accesses. Signed-off-by:
-
Geert Uytterhoeven authored
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since commits c0b2d75d ("clk: renesas: cpg-mssr: Add R8A7743 support") and 9127d54b ("clk: renesas: cpg-mssr: Add R8A7745 support"). Signed-off-by:
-
Geert Uytterhoeven authored
Document properties needed to use the Reset Control feature of the Renesas Clock Pulse Generator / Module Standby and Software Reset module. Signed-off-by: -
Geert Uytterhoeven authored
As the function header of cpg_mstp_clock_register() is split in an unusual way, "git diff" gets confused when changes to the body of the function are made, and attributes them to the wrong function. Reformat the function header to fix this. Signed-off-by:
-
Pierre-Louis Bossart authored
s/Acumulate/Accumulate/ Signed-off-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
-
Irina Tirdea authored
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate. For example, the usage for platform clocks suggested in the datasheet is the following: PLT_CLK[0..2] - Camera PLT_CLK[3] - Audio Codec PLT_CLK[4] - PLT_CLK[5] - COMMs Signed-off-by:
Irina Tirdea <irina.tirdea@intel.com> Signed-off-by:
-
