- 09 Feb, 2021 40 commits
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Wyatt Wood authored
[Why] Since dmub_rb_cmds are not initialized to 0, the header is filled with invalid data. This is causing issues on the fw side. [How] Initialize dmub_rb_cmd unions to 0. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lang Yu authored
Replace "/" with div_u64 for 64bit division on 32bit OS. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Eric Yang authored
[Why] At SW init, we may not be ready to do detect eDP sink. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jun Lei authored
3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] Current implementation of mod_hdcp_hdcp2_validate_ake_cert() does not process HDCP status message TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR. As a result, when there is a signature certificate error, mod_hdcp_hdcp2_validate_ake_cert would return the default status, which is success. [How] For all messages other than TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS and TA_HDCP2_MSG_AUTHENTICATION_STATUS__RECEIVERID_REVOKED, return status as failure. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Derek Lai authored
[Why and How] VBIOS program DIG_CLK_PATTERN using engine ID instead of PHY ID. Workaround by writing value for 0x1f (for HDMI) after calling vbios. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Fangzhi Zuo authored
Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Tao Zhou authored
As dimgrey_cavefish driver is stable enough, set gpu recovery as default in HW hang for dimgrey_cavefish. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by:
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Kenneth Feng authored
Enable LCLK deep sleep and it works if we enable ASPM: modprobe amdgpu aspm=1 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
If device suspend fails when we attempt to runtime suspend, reset the runpm flag. Acked-by:
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Alex Deucher authored
the flag used by kfd is not actually related to fbcon, it just happens to align. Use the runpm flag instead so that we can decouple it from the fbcon flag. v2: fix resume as well Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Acked-by:
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Alex Deucher authored
These are already called in amdgpu_device_suspend/resume which are already called in the same functions. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by:
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Alex Deucher authored
This allows us to use generic PCI reset mechanisms (FLR, SBR) as a reset mechanism to verify that the generic PCI reset mechanisms are working properly. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Alex Deucher authored
Drop duplicate reset method logging, whitespace changes. Acked-by:
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Xiaomeng Hou authored
Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by:Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Xiaomeng Hou authored
The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by:
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Xiaomeng Hou authored
Add PP messages for reading/setting Fast PPT and Slow PPT limit. Signed-off-by:
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Nirmoy Das authored
To achieve the best QoS for high priority compute jobs it is required to limit waves on other compute pipes as well. This patch will set min value in non high priority mmSPI_WCL_PIPE_PERCENT_CS[0-3] registers to minimize the impact of normal/low priority compute jobs over high priority compute jobs. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Wayne Lin authored
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
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Wayne Lin authored
[Why & How] In order to get appropriate timing for registers which read/write is vertical line sensitive, add new IRQ source variable. This interrupt is triggered by specific vertical line, Signed-off-by:
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Kevin Wang authored
simplify the list operation. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Kevin Wang authored
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by:
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Likun Gao authored
Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by:
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Likun Gao authored
Implement smuio v11_0_6 callbacks which will used by Sienna_Cichlid and forward ASIC. Signed-off-by:
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Likun Gao authored
Signed-off-by:
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Likun Gao authored
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by:
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Kenneth Feng authored
Enable DCS V1: Enable Async DCS. V2: Add the ppfeaturemask bit to enable from the modprobe parameter. V3: 1. add the flag to skip APU support. 2. remove the hunk for workload selection since it doesn't impact the function. Signed-off-by:
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Alex Deucher authored
The hw interface changed on arcturus so the old numbering scheme doesn't work. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Align with Vangogh. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1467Acked-by:
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Kent Russell authored
Instead of caching the value during amdgpu_device_init, just call the function directly. This avoids issues where the unique_id hasn't been saved by the time that KFD's topology snapshot is done (e.g. Arcturus). KFD's topology information from the amdgpu_device was initially cached at KFD initialization due to amdkfd and amdgpu being separate modules. Now that they are combined together, we can directly call the functions that we need and avoid this unnecessary duplication and complexity. As a side-effect of this change, we also remove unique_id=0 for CPUs, which is obviously not unique. v2: Drop previous patch printing unique_id in hex Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Kenneth Feng authored
The power limit and clock ragne are different in AC mode and DC mode. Firmware does the setting after this feature is enabled. Signed-off-by:
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Nirmoy Das authored
Enable gfx wave limiting for gfx jobs before pushing high priority compute jobs so that high priority compute jobs gets more resources to finish early. v2: use ring priority instead of job priority. Signed-off-by:
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Nirmoy Das authored
Wave limiting can be use to load balance high priority compute jobs along with gfx jobs. When enabled, this will reserve ~75% of waves for compute jobs. We do not need this from gfx10 onwards because >=gfx10 has asynchronous compute tunneling to replace wave limit requirement. Signed-off-by:
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Nirmoy Das authored
For high priority compute to work properly we need to enable wave limiting on gfx pipe. Wave limiting is done through writing into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high priority compute queue to avoid race condition between multiple high priority compute queues writing that register simultaneously. Signed-off-by:
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