- 15 Jun, 2022 12 commits
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Chengming Gui authored
This reverts commit 2cfe34e1. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Enable BAMACO reset support for SMU 13.0.0. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
The feature is ready with latest PMFW and IFWI. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] To reduce stack usage, move some variables into heap in the DML function dml32_ModeSupportAndSystemConfigurationFull() Fixes: dda4fb85 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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Leo Li authored
[Why] There is a theoretical problem in prior patches for reducing the stack size of *update_bw_bounding_box() functions. By modifying the soc.clock_limits[n] struct directly, this can cause unintended behavior as the for loop attempts to swap rows in clock_limits[n]. A temporary struct is still required to make sure we stay functinoally equivalent. [How] Add a temporary clock_limits table to the SOC struct, and use it when swapping rows. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Michel Dänzer authored
The commit below changed the TTM manager size unit from pages to bytes, but failed to adjust the corresponding calculations in amdgpu_ioctl. Fixes: dfa714b8 ("drm/amdgpu: remove GTT accounting v2") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930 Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642Tested-by:
Martin Roukala <martin.roukala@mupuf.org> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Tim Huang authored
The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Tim Huang authored
For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different, we need this to correct the reading address. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] There are cases where swizzle modes are set but modifiers arent. For such a userspace, we need not check modifiers while checking compatibilty in the drm hook for checking plane format. Ignore checking modifiers but check the DCN generation for the supported swizzle mode. v2: squash in unused variable removal (Alex) Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Yifan Zhang authored
GPA mode should be disabled in direct load. Signed-off-by:
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Yifan Zhang authored
Enable vcn/jpeg 4_0_2. Signed-off-by:
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Yang Wang authored
issue calltrace: [ 402.773695] [drm] failed to load ucode SMC(0x2C) [ 402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0) [ 402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed! [ 402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring [ 402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed [ 402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22 [ 402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed [ 402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init if not reset mp1 state during kernel driver unload, it will cause psp load pmfw fail at the second time. add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7 Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
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- 10 Jun, 2022 13 commits
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Kenneth Feng authored
support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO for the low latency, and it only happens on specific platforms. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Kenneth Feng authored
enable gfxoff on smu_v13_0_7 Signed-off-by:
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Kenneth Feng authored
update the driver if header for smu_v13_0_7 Signed-off-by:
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Andrey Grodzovsky authored
We skip rest requests if another one is already in progress. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by:
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Andrey Grodzovsky authored
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by:
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Andrey Grodzovsky authored
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by:
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Andrey Grodzovsky authored
Save the extra usless work schedule. Signed-off-by:
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Andrey Grodzovsky authored
Will be read by executors of async reset like debugfs. Signed-off-by:
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Andrey Grodzovsky authored
This reverts commit 6417250d. amdpgu need this function in order to prematurly stop pending reset works when another reset work already in progress. Acked-by:
Tejun Heo <tj@kernel.org> Signed-off-by:
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Ramesh Errabolu authored
The field is redundant and does not serve any functional role Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Chandan Vurdigere Nataraj authored
[Why] Getting below build errors: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1535:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:3276:20: error: variable 'v1_5' is uninitialized when used here [-Werror,-Wuninitialized] for (i = 0; i < v1_5->number_of_path; ++i) ^~~~ [How] Fix compilation issues Signed-off-by:Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com> Reviewed-by:
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Chandan Vurdigere Nataraj authored
[Why] Getting below errors: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] mode_lib->vba.SourceScan[k], ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1744:22: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) { ~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 errors generated. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:5484:18: error: implicit conversion from enumeration type 'RequestType' to different enumeration type 'enum RequestType' [-Werror,-Wenum-conversion] RequestLuma = REQ_256Bytes; ~ ^~~~~~~~~~~~ 18 errors of similar kind [How] 1. Add typecast at relevant places 2. Move the enum RequestType definition ahead of declarations Signed-off-by:
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- 08 Jun, 2022 15 commits
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Christian König authored
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146 ("drm/amdgpu: rework TLB flushing") Reviewed-by:
Michal Kubecek <mkubecek@suse.cz> Signed-off-by:
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Christian König authored
The job is not yet initialized here. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Kenneth Feng authored
enable BACO on smu_v13_0_7 Signed-off-by:
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Kenneth Feng authored
add interface to deallocate power_context for smu_v13_0_7 Signed-off-by:
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Mohammad Zafar Ziya authored
Add jpeg vmid update under IB submit Signed-off-by:
Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Yifan Zhang authored
invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0 Signed-off-by:
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Evan Quan authored
PMFW will handle that properly. Driver involvement may cause some unexpected issues. Signed-off-by:
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Evan Quan authored
Drop those redundant declarations in smu_v13_0.h. Signed-off-by:
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Evan Quan authored
Fulfill the interfaces for mode1 reset related. Signed-off-by:
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Evan Quan authored
Make sure the clockgating feature is supported before action. Otherwise, the feature may be disabled unexpectedly on enablement request. Signed-off-by:
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Evan Quan authored
Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by:
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Evan Quan authored
Drop extra CMN2ASIC_MAPPING_FEATURE transform. Also some cosmetic fixes for better readability. Signed-off-by:
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Evan Quan authored
As there is actually no direct dependence between them. Signed-off-by:
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Evan Quan authored
The new 78.40.0 PMFW has this feature supported. Signed-off-by:
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ZhenGuo Yin authored
The scratch register should be accessed through MMIO instead of RLCG in SRIOV, since it being used in RLCG register access function. Fixes: d54762cc ("drm/amdgpu: nuke dynamic gfx scratch reg allocation") Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Reviewed-by:
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