- 14 Dec, 2018 1 commit
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Jon Hunter authored
The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 25 Jul, 2018 3 commits
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Peter De-Schrijver authored
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by:
Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
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Peter De Schrijver authored
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by:
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Aapo Vienamo authored
Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by:
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- 18 May, 2018 1 commit
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Dmitry Osipenko authored
CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
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- 08 Mar, 2018 1 commit
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Peter De Schrijver authored
To ensure writes to clock registers have properly propagated through the clock control logic and state machines, we need to ensure the writes have been posted in the registers and wait for 1us after that. Signed-off-by:
Hector Martin <marcan@marcan.st> Tested-by:
Andre Heider <a.heider@gmail.com> Tested-by:
Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by:
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- 19 Oct, 2017 1 commit
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Thierry Reding authored
There is a common pattern that registers individual peripheral clocks from an initialization table. Add a common implementation to remove the duplication from various call sites. Signed-off-by:
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- 23 Aug, 2017 1 commit
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Alex Frid authored
Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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- 20 Mar, 2017 4 commits
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Thierry Reding authored
The recent conversion of proper const usage was only partial and didn't include Tegra20 and Tegra30 support. Fix that up. Signed-off-by: -
Peter De Schrijver authored
Add a super clock type which implements both mux and divider. This is used for aclk. Signed-off-by:
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Peter De Schrijver authored
checkpatch now warns for const ** and expects const * const * to be used instead. This means we have to update the prototypes and function declarations to handle this change. Signed-off-by:
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Peter De Schrijver authored
When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by:
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- 30 Jun, 2016 1 commit
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Andrew Bresticker authored
Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by:Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by:
Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by:
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- 28 Apr, 2016 3 commits
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Rhyland Klein authored
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by:
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Thierry Reding authored
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: -
Thierry Reding authored
The peripheral clock registers are defined in static tables. These tables never need to be modified at runtime, so they can reside in read-only memory. Signed-off-by:
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- 17 Dec, 2015 8 commits
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Rhyland Klein authored
Implement clock support for Tegra210. Signed-off-by:
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Bill Huang authored
Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by:
Bill Huang <bilhuang@nvidia.com> Signed-off-by:
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Bill Huang authored
Add some logic for Spread Spectrum control. It is used in conjuncture with SDM fractional dividers. SSC has to be disabled when we configure the divider settings. Signed-off-by:
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Rhyland Klein authored
Add a callback to the pll_params for custom dynamic ramping functions which can be specified per PLL. Reviewed-by:
Benson Leung <bleung@chromium.org> Signed-off-by:
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Bill Huang authored
Add logic which (if specified for a pll) can verify that a PLL is set to the proper default value and if not can set it. This can be specified per PLL as each will have different default values. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by:
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Bill Huang authored
This code makes use of the SDM fractional divider if present to constrain the allowable programming range of the PLL divider register bitfields to take advantage of higher frequency granularity that can be induced by the SDM divider. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by:
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Rhyland Klein authored
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register and handle PLLMB. PLLMB is used to allow switching between 2 PLLM's without having to use and intermediate backup PLL, as we need to lock the PLL before we can switch to it. Reviewed-by:
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Rhyland Klein authored
On Tegra210 SoC's, the logic to enable several of the plls is different from previous generations. Therefore, add registration functions specific to Tegra210 which will handle them appropriately. Reviewed-by:
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- 20 Nov, 2015 6 commits
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Bill Huang authored
If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths. Reviewed-by:
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Rhyland Klein authored
For Tegra210, the logic to calculate out-of-table rates is different from previous generations. Add callbacks that can be overridden to allow for different ways of calculating rates. Default to _cal_rate when not specified. This patch also includes a new flag which is used to set which method of fixed_mdiv calculation is used. The new method for calculating the fixed divider value for M can be more accurate especially when fractional dividers are in play. This allows for older chipsets to use the existing logic and new generations to use a newer version which may work better for them. Based on original work by Aleksandr Frid <afrid@nvidia.com> Reviewed-by:
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Rhyland Klein authored
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into the equation to calculate the effective N value for PLL which supports fractional divider. The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer feedback divider. Reviewed-by:
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Bill Huang authored
New SoC's may have more than 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Reviewed-by:
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Rhyland Klein authored
Create a wrapper interface to make use of the existing clk_pll_wait_for_lock. This will be useful for implementations of callbacks in Tegra SoC specific clock drivers. Reviewed-by:
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Thierry Reding authored
This is static data that is never modified, so make it const. Signed-off-by:
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- 20 Oct, 2015 3 commits
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Rhyland Klein authored
tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by:
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Thierry Reding authored
Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by:
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Rhyland Klein authored
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params struct. Update the struct comments to reflect where the fields really are. Signed-off-by:
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- 16 Jul, 2015 1 commit
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Mikko Perttunen authored
This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset control with number >= num_periph_banks * 32 is attempted to be asserted or deasserted respectively. Numbers greater than or equal to num_periph_banks * 32 are used to avoid clashes with low numbers that are automatically mapped to standard CAR reset lines. Each SoC with these special resets should specify the defined reset control numbers in a device tree header file. Signed-off-by:
Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by:
Michael Turquette <mturquette@linaro.org> Signed-off-by:
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- 13 May, 2015 2 commits
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Thierry Reding authored
The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: -
Mikko Perttunen authored
The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by:
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- 10 Apr, 2015 2 commits
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Thierry Reding authored
Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: -
Thierry Reding authored
The clock initialization structure is named struct clk_init_table. Update the kerneldoc comment to use the correct name. Reviewed-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
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- 26 Nov, 2014 1 commit
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Thierry Reding authored
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By:
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- 11 Dec, 2013 1 commit
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Stephen Warren authored
Now that no code uses the custom Tegra module reset API, we can remove its implementation. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
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