- 11 Mar, 2016 40 commits
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Dennis Dalessandro authored
Query gid is in rdmavt, but still relies on the driver to maintain the guid table. Add the necessary driver call back and remove the existing verb handler. Reviewed-by:
Harish Chegondi <harish.chegondi@intel.com> Signed-off-by:
Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by:
Doug Ledford <dledford@redhat.com>
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Jubin John authored
Clean up init_cntrs() by removing unnecessary memsets and debug statements Suggested-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by:
Jubin John <jubin.john@intel.com> Signed-off-by:
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Dean Luick authored
The LRH has a 12 bit packet length field, not 11 bit. This caused a snoop packet length miscalculation leading to a crash when sending a large ping over IPoIB while running opapacketcapture. Reviewed-by:
Dean Luick <dean.luick@intel.com> Signed-off-by:
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Dean Luick authored
Change the TWSI reset function so it will stop the reset once the lines are in an expected state. Reviewed-by:
Easwar Hariharan <easwar.hariharan@intel.com> Reviewed-by:
Pablo Cacho <pablo.cacho@intel.com> Signed-off-by:
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Dean Luick authored
There are several reasons why PCIE AER cannot be enabled. Do not report the failure to enable as an error. Reviewed-by:
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Easwar Hariharan authored
This patch implements LED beaconing for maintenance. A MAD packet with the LEDInfo attribute set to 1 will enable LED beaconing with a duty cycle of 2s on and 1.5s off. A MAD packet with the LEDInfo attribute set to 0 will disable beaconing and return the LED to normal operation. Reviewed-by:
Mitko Haralanov <mitko.haralanov@intel.com> Signed-off-by:
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Dean Luick authored
Copy the last 8 bytes of user mode RC WRITE_ONLY and WRITE_LAST opcodes separately from the rest of the data. It is a de-facto standard for some MPI implementations to use a poll on the last few bytes of a verbs message to indicate that the message has been received rather than follow the required function method. The driver uses the kernel memcpy routine, which becomes "rep movsb" on modern machines. This copy, while very fast, does not guarantee in-order copy completion and the result is an occasional perceived corrupted packet. Avoid the issue by splitting the last 8 bytes to copy from the verbs opcodes where it matters and performing an in-order byte copy. Reviewed-by:
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Dean Luick authored
A host fabric serdes reset is required to go back to polling. However, access to the fabric serdes may have been invalidated by the sibling HFI when it downloads its fabric serdes firmware. Work around this by re-downloading and re-validating the serdes firmware at reset time on Bx hardware. Reviewed-by:
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Dean Luick authored
Make physical state change reporting be per-device, not global to reduce excessive reports of "physical state changed" Reviewed-by:
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Mitko Haralanov authored
To ensure correct operation between the driver and PSM with respect to managing the SDMA request ring, it is important that the status for a particular request slot is set at the correct time. Otherwise, PSM can get out of sync with the driver, which could lead to hangs or errors on new requests. Properly determining of when to set the error status of a SDMA slot depends on knowing exactly when the last txreq for that request has been completed. This in turn requires that the driver knows exactly how many requests have been generated and how many of those requests have been successfully submitted to the SDMA queue. The previous implementation of the mid-layer SDMA API did not provide a way for the caller of sdma_send_txlist() to know how many of the txreqs in the input list have actually been submitted without traversing the list and counting. Since sdma_send_txlist() already traverses the list in order to process it, requiring such traversal in the caller is completely unnecessary. Therefore, it is much easier to enhance sdma_send_txlist() to return the number of successfully submitted txreqs. This, in turn, allows the caller to accurately determine the progress of the SDMA request and, therefore, correctly set the error status at the right time. Reviewed-by:
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Dean Luick authored
At the end of the packet processing interrupt and thread handler, the RcvAvail interrupt is finally cleared down. There is a window between the last packet check (via DMA to memory) and interrupt clear-down. The code to recheck for a packet once the RcvAVail interrupt is enabled must ultimately use a CSR read of RcvHdrTail rather than depend on DMA'ed memory. This change adds a CSR read of RcvHdrTail if the memory check does not show a packet preset. The memory check is retained as a quick test before doing the more expensive, but always correct, CSR read. In the ASIC, the CSR read used to force the RcvAvail clear-down write to complete may bypass queued DMA writes to memory. The only correct way to decide if a packet has arrived without an interrupt to push DMA to memory ahead of itself is to read the tail directly after RcvAvail has been cleared down. It is not sufficient to just read the tail and skip pushing the clear-down. Both must be done. The tail read will not push clear-down write due to it being in a different area of the chip. At this point, it is OK to have packet data still being DMA'ed to memory. This is the end of packet processing for previous packets. If the driver detects a new packet has arrived before interrputs were re-enabled, it will force a new interrupt and the interrupt will push the packet DMAs to memory, where the driver will then react to the interrupt and do normal packet processing. Reviewed-by:
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Mitko Haralanov authored
Commit a0d40693 ("staging/rdma/hfi1: Add page lock limit check for SDMA requests") added a mechanism to delay the clean-up of user SDMA requests in order to facilitate proper locked page counting. This delayed processing was done using a kernel workqueue, which meant that a kernel thread would have to spin up and take CPU cycles to do the clean-up. This proved detrimental to performance because now there are two execution threads (the kernel workqueue and the user process) needing cycles on the same CPU. Performance-wise, it is much better to do as much of the clean-up as can be done in interrupt context (during the callback) and do the remaining work in-line during subsequent calls of the user process into the driver. The changes required to implement the above also significantly simplify the entire SDMA completion processing code and eliminate a memory corruption causing the following observed crash: [ 2881.703362] BUG: unable to handle kernel NULL pointer dereference at (null) [ 2881.703389] IP: [<ffffffffa02897e4>] user_sdma_send_pkts+0xcd4/0x18e0 [hfi1] [ 2881.703422] PGD 7d4d25067 PUD 77d96d067 PMD 0 [ 2881.703427] Oops: 0000 [#1] SMP [ 2881.703431] Modules linked in: [ 2881.703504] CPU: 28 PID: 6668 Comm: mpi_stress Tainted: G OENX 3.12.28-4-default #1 [ 2881.703508] Hardware name: Intel Corporation S2600KP/S2600KP, BIOS SE5C610.86B.11.01.0044.090 [ 2881.703512] task: ffff88077da8e0c0 ti: ffff880856772000 task.ti: ffff880856772000 [ 2881.703515] RIP: 0010:[<ffffffffa02897e4>] [<ffffffffa02897e4>] user_sdma_send_pkts+0xcd4/0x [ 2881.703529] RSP: 0018:ffff880856773c48 EFLAGS: 00010287 [ 2881.703531] RAX: 0000000000000000 RBX: 0000000000001000 RCX: 0000000000002000 [ 2881.703534] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000002000 [ 2881.703537] RBP: 0000000000000000 R08: 0000000000000001 R09: 0000000000000000 [ 2881.703540] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000 [ 2881.703543] R13: 0000000000000000 R14: ffff88071e782e68 R15: ffff8810532955c0 [ 2881.703546] FS: 00007f9c4375e700(0000) GS:ffff88107eec0000(0000) knlGS:0000000000000000 [ 2881.703549] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2881.703551] CR2: 0000000000000000 CR3: 00000007d4cba000 CR4: 00000000003407e0 [ 2881.703554] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 2881.703556] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 2881.703558] Stack: [ 2881.703559] ffffffff00002000 ffff881000001800 ffffffff00000000 00000000000080d0 [ 2881.703570] 0000000000000000 0000200000000000 0000000000000000 ffff88071e782db8 [ 2881.703580] ffff8807d4d08d80 ffff881053295600 0000000000000008 ffff88071e782fc8 [ 2881.703589] Call Trace: [ 2881.703691] [<ffffffffa028b5da>] hfi1_user_sdma_process_request+0x84a/0xab0 [hfi1] [ 2881.703777] [<ffffffffa0255412>] hfi1_aio_write+0xd2/0x110 [hfi1] [ 2881.703828] [<ffffffff8119e3d8>] do_sync_readv_writev+0x48/0x80 [ 2881.703837] [<ffffffff8119f78b>] do_readv_writev+0xbb/0x230 [ 2881.703843] [<ffffffff8119fab8>] SyS_writev+0x48/0xc0 This commit also addresses issues related to notification of user processes of SDMA request slot availability. The slot should be cleaned up first before the user processes is notified of its availability. Reviewed-by:
Arthur Kepner <arthur.kepner@intel.com> Reviewed-by:
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Dean Luick authored
When writing to the EPROM, the driver will always use the "first" device. This is incorrect for multiple cards. Use the device file minor to determine the device to use. Reject the generic device file. Reviewed-by:
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Easwar Hariharan authored
The syslog message causes unnecessary alarm for the single and dual port x8 cards by reporting at an error level. This patch reduces the severity to informational only and adds speed information. Reviewed-by:
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Mitko Haralanov authored
When TID caching was enabled, the way the driver found RB nodes when PSM was unprogramming TID entries was by traversing the RB tree, looking for a match on the RcvArray entry index. The performance of this algorithm was not only poor but also inconsistent depending on how many RB nodes would have to be traversed before a match was found. The lower performance was especially evident in cases where there was a cache miss with the cache full, requiring the unprogramming of several TID entries. This commit changes how RB nodes are looked up when being free'd by PSM to a index-based lookup into a flat array on the index of the RcvArray entry. This turns the entire look-up process into an O(1) algorithm. Special care needs to be taken for situations when TID caching is disabled. In those cases, there is no need to insert the RB nodes into an actual RB tree. Since the entire RcvArray management mechanism is managed by an index-based algorithm, the RB nodes can be saved into the flat array, making both "insertion" and "removal" faster. Reviewed-by:
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Sebastian Sanchez authored
The driver crashes when loaded with parameter rcvhdrcnt=2097152. The root cause was that rcvhdrcnt was initially a 32 bit variable and its value was assigned to a 16 bit variable, truncating the upper 16 bits. This patch prevents the user from passing a value for rcvhdrcnt greater than 16352 (Maximum number for rcvhdrcnt). Reviewed-by:
Sebastian Sanchez <sebastian.sanchez@intel.com> Signed-off-by:
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Vennila Megavannan authored
This patch fixes the fairness issues in QP scheduling - the timeout for cond_resched is changed to a ratio of qp->timeout_jiffies - workqueue_congested is used to determine if qp needs to reschedule itself Reviewed-by:
Vennila Megavannan <vennila.megavannan@intel.com> Signed-off-by:
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Dean Luick authored
The original I2C interface was geared for QSFP accesses. Modify the interface to behave more like a generic I2C controller such that reads and writes can accept multi-byte offsets. Removed reads following writes and moved reset to top level. Reviewed-by:
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Vennila Megavannan authored
A patch to fix fairness issues in QP scheduling requires n_send_schedule counter to be converted to a per cpu counter to reduce cache misses. Reviewed-by:
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Mitko Haralanov authored
Change verbs memory allocations to the device numa node. This keeps memory close to the device for optimal performance. Reviewed-by:
Ira Weiny <ira.weiny@intel.com> Signed-off-by:
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Mitko Haralanov authored
Allocate the user mode send context memory on the numa node which the device is attached to for better performance. Reviewed-by:
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Mitko Haralanov authored
This patch unifies the affinity support for CPU and IRQ allocations into a single code base. The goal is to allow the driver to make intelligent placement decision based on an overall view of processes and IRQs across as much of the driver as possible. Pulling all the scattered affinity code into a single code base lays the ground work for accomplishing the above goal. For example, previous implementations made user process placement decision solely based on other user processes. This algorithm is limited as it did not take into account IRQ placement and could result in overloading certain CPUs. A single code base also provides a much easier way to maintain and debug any performance issues related to affinity. Reviewed-by:
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Mitko Haralanov authored
struct hfi1_devdata contained 2 variables which represented the numa node the device is attached to. Remove the duplicated one. Reviewed-by:
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Mitko Haralanov authored
This comment and code was unused. Just remove it. Reviewed-by:
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Ira Weiny authored
SLs which are mapped to SC15 are invalid and should fail the operation. For RC/UC QP types, verify the AH information at modify_qp time and fail the modify_qp if the SL is invalid. For other QP types check the SL during post_send via the new rdmavt callback. Reviewed-by:
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Ashutosh Dixit authored
hfi1 HW has a high PCIe ASPM L1 exit latency and also advertises an acceptable latency less than actual ASPM latencies. Additional mechanisms than those provided by BIOS/OS are therefore required to enable/disable ASPM for hfi1 to provide acceptable power/performance trade offs. This patch adds this support. By means of a module parameter ASPM can be either (a) always enabled (power save mode) (b) always disabled (performance mode) (c) enabled/disabled dynamically. The dynamic mode implements two heuristics to alleviate possible problems with high ASPM L1 exit latency. ASPM is normally enabled but is disabled if (a) there are any active user space PSM contexts, or (b) for verbs, ASPM is disabled as interrupt activity for a context starts to increase. A few more points about the verbs implementation. In order to reduce lock/cache contention between multiple verbs contexts, some processing is done at the context layer before contending for device layer locks. ASPM is disabled when two interrupts for a context happen within 1 millisec. A timer is scheduled which will re-enable ASPM after 1 second should the interrupt activity cease. Normally, every interrupt, or interrupt-pair should push the timer out further. However, since this might increase the processing load per interrupt, pushing the timer out is postponed for half a second. If after half a second we get two interrupts within 1 millisec the timer is pushed out by another second. Finally, the kernel ASPM API is not used in this patch. This is because this patch does several non-standard things as SW workarounds for HW issues. As mentioned above, it enables ASPM even when advertised actual latencies are greater than acceptable latencies. Also, whereas the kernel API only allows drivers to disable ASPM from driver probe, this patch enables/disables ASPM directly from interrupt context. Due to these reasons the kernel ASPM API was not used. Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
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Vennila Megavannan authored
Add a per port sysfs paramter to toggle cc_prescan/Fast ECN Detection and remove the Kconfig option which was previously used to control this. While am updating the sysfs documentation, fix the name of CCMgtA. Reviewed-by:
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Mitko Haralanov authored
The RcvCtxtCtrl register was being incorrectly set upon context initialization and clean up resulting, in many cases, of contexts using settings from previous contexts' initialization. This resulted in bad and unexpected behavior. This was especially important for the TailUpd bit, which requires special handling and if set incorrectly could lead to severely degraded performance. This patch fixes the handling of the RcvCtxtCtrl register, ensuring that each context gets initialized with settings applicable only for that context. It also ensures the proper setting for the TailUpd bit by setting it to either 0 or 1 (as needed by the context's configuration) explicitly. Reviewed-by:
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Sebastian Sanchez authored
When 32-bit hardware counters overflow, hfi1stats misinterprets the counters as being 64 bits causing the deltas for the counters to be a huge number. This patch makes hfi1stats aware that a counter is 32 bits by making the driver write <counter name>,32 to debugfs. Reviewed-by:
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Dean Luick authored
The simulator does not correctly handle LCB cclk loopback. Skip that step for simulation - it is not needed. Reviewed-by:
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Dean Luick authored
Simulation has no firmware, so it will never move firmware acquire to the FINAL state. Avoid that by skiping the TRY state and moving directly to FINAL. Reviewed-by:
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Easwar Hariharan authored
Loopback plugs used for testing hardware don't need to be qualified to bring the link up unlike production cables. This patch adds an exception for loopback plugs to the QSFP and SerDes tuning algortihm. Reviewed-by:
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Dean Luick authored
Make firmware validation failure and missing firmware messages a warning since alternates can be tried. Add an error message when all attempts fail. Reviewed-by:
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Dean Luick authored
Change-Id: Icc4ad27c4c67e51df8c8a203c4f16973793678ec Reviewed-by:
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Mike Marciniszyn authored
Implement per-VL transmit counters. Not all errors can be attributed to a particular VL, so make a best attempt. o Extend the egress error bits used to count toward transmit discard. o When an egress error or send error occur, try to map back to a VL. o Implement a SDMA engine to VL (back) map. o Add per-VL port transmit counters Reviewed-by:
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Dean Luick authored
The gen3 bump code must mark a firmware download failure as fatal. Otherwise a later load attempt will fail with a NULL dereference. Also: o Only do a firmware back-off for RTL. There are no alternates for FPGA or simulation. o Rearrange OS firmware request order to match what is actually loaded. This results in more coherent informational messages in the case of missing firmware. Reviewed-by:
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Easwar Hariharan authored
This patch implements support for turning on and off the clock data recovery mechanisms implemented in QSFP cable on request by the DC 8051 on a per-lane basis. Reviewed-by:
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Easwar Hariharan authored
The current code employs a heuristic to guess the port type. The canonical location to identify the port type of the designed platform is from the platform configuration data. This patch uses the previously fetched port type from the platform configuration and removes the now obsolete heuristic routine and its associated defines. Reviewed-by:
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Easwar Hariharan authored
This patch qualifies and tunes active and optical cables for optimal bit error rate and signal integrity settings. These settings are fetched from the platform configuration data. Based on attributes of the QSFP cable as read from the SFF-8636 compliant memory map, we select the appropriate settings from the platform configuration data (examples: TX/RX equalization, enabling cable high power, enabling TX/RX clock data recovery mechanisms, and RX amplitude control) and apply them to the SERDES and QSFP cable. The platform configuration data also contains system parameters such as maximum power dissipation supported, and the cables are qualified based on these parameters. As part of qualifying the cables, the correct OfflineDisabledReasons are set for the appropriate scenarios. Reviewed-by:
Brent R Rothermel <brent.r.rothermel@intel.com> Signed-off-by:
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Mike Marciniszyn authored
The QSFP memory cache reads both lower and upper page 0H in one shot, which leads to the address counter wrapping around to the beginning of lower page 00H at byte 128, as defined by SFF-8636. This patch fixes this by modifying the underlying QSFP read and writes to avoid this wrap around. Reviewed-by:
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