- 08 Jun, 2021 40 commits
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Rohit Khaire authored
This is similar to IH_RB_CNTL programming in navi10_ih_toggle_ring_interrupts Signed-off-by:
Rohit Khaire <rohit.khaire@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Wyatt Wood authored
Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Po-Ting Chen authored
[Why] To support a new visual confirm mode: swizzle to show the specific color at the screen border according to different surface swizzle mode. Currently we only support the Linear mode with red color. Signed-off-by:
Po-Ting Chen <robin.chen@amd.com> Acked-by:
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Dingchen (David) Zhang authored
[WHY] - Commit from userspace could cause link stream to disable and hdcp auth to reset when the HDCP has already been enabled at the moment. CP should fall back to DESIRED from ENABLED in such cases. - This change was previously reverted due to a regression caused, which has now been cleared. [HOW] In hdcp display removal, change CP to DESIRED if at the moment CP is ENABLED before the auth reset and removal of linked list element. Signed-off-by:
Dingchen (David) Zhang <dingchen.zhang@amd.com> Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Eric Bernstein authored
[Why] There is an assert in cases where transition from ODM 2:1 to ODM 1:1 (bypass) [How] Remove assert since this case is now valid. Update diags tests for ODM transitions. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Roy Chan authored
[Why] Found a use case (IPKVM) that DP-VGA active dongle does not return any EDID and the mentioned commit broke it. [How] This reverts "Disconnect non-DP with no EDID" Signed-off-by:
Roy Chan <roy.chan@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Fangzhi Zuo authored
[Why & How] Add debugfs entry to force dsc decoding at PCON when DSC capable external RX is connected. In such case, it is free to test DSC decoding at external RX or at PCON. Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Aric Cyr authored
[Why] When calculating recout width for an MPO plane on a mode that's using ODM combine, driver can calculate a negative value, resulting in a crash. [How] For negative widths, use zero such that validation will prune the configuration correctly and disallow MPO. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] For DCN30 and later, there is no data in DML arrays indexed by state at index num_states. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Wesley Chalmers authored
[WHY] DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back. Signed-off-by:
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Wesley Chalmers authored
[WHY] HW has handed down a new sequence that requires access to these registers. v2: squash in DCN3.1 fixes (Alex) Signed-off-by:
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Wesley Chalmers authored
[WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] Rearranging pipes with multiple displays and multiple planes cannot be done atomically and requires a much improved sequence to deal with it. [How] To workaround such issues, prefer avoid pipe-split policy for multidisplay scenarios. Signed-off-by:
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Vladimir Stempen authored
[why] When OS overrides training link training parameters for MST device to SST mode, MST resources are not released and leak of the resource may result crash and incorrect MST discovery during following hot plugs. [how] Retaining sink object to be reused by SST link and releasing MST resources. Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Mikita Lipski authored
[why] Allow specifying which panel to take PSR Residency measurements from. [how] Pass panel instance to DMUB through GPINT in the upper 8 bits of the parameter. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Jayendran Ramani authored
[How] Add call to get the last used VTOTAL from DC Signed-off-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why & How] SET_CONFIG transactions with DMUB is not used and removed. Signed-off-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Roman Li authored
[Why] We update scaling settings when scaling mode has been changed. However when changing mode from native resolution the scaling mode previously set gets ignored. [How] Perform scaling settings update on modeset. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why & How] Add support for transmitting training pattern sequences for links whose encoders have been dynamically assigned. Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why & How] Add functionality useful for DP equalization phase of link training to public interface. Signed-off-by:
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Ilya Bakoulin authored
[Why] This change was found to break some high-refresh modes. Reverting to unblock mainline. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Evgenii Krasnikov authored
[WHY] Currently there is no way to visually identify if there is one or more layers presented fullscreen on the display [HOW] Add new visual confirm colors in get_surface_visual_confirm_color for planes with layer_index > 0 Signed-off-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why + How] Visual confirm has no asic-specific logic, so we can refactor and unify these functions that are currently spread out across multiple dcn files. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. This will allow visual confirm to updated independently of MPCC blending updates. v2: squash in DCN3.1 fixes Signed-off-by:
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JinZe.Xu authored
[Why] This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs. [How] Power gating is controlled by driver. Signed-off-by:
JinZe.Xu <JinZe.Xu@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] DSCCLK validation is not necessary because DSCCLK is derrived from DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too. Doing DSCLK validation in addition to DISPCLK leads to modes being wrongly rejected when DSCCLK was incorrectly set outside of DML. [how] Remove DSCCLK validation because it's implicitly validated under DISPCLK Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Some DPRX will issue CP_IRQ when user disconnects a display that has been authenticated. Since display is being disconnecting dpcd read will fail. This will cause us to attempt HDCP retry on disconnection. We are adding a 100ms delay before retry. So we will only start retry if within 100ms there is no disconnection call to HDCP module. Signed-off-by:
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Mikita Lipski authored
[why] Updating PSR interfaces to allow PSR enablement per eDP panel. [how] - Copying PSR command structures to DC - Changing function interfaces to pass panel instance - Communicating with DMUB per link instead of assuming to use a single one -Iterating through all PSR capable panels when enabling/disabling all Signed-off-by:
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Jake Wang authored
[Why] During DCC on/off, stutter period is calculated before DCC has fully transitioned. This results in incorrect stutter period calculation. [How] Trigger a full update when DCC changes between on/off. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Zhigang Luo authored
psp added new feature to check fw buffer address for sriov vf. the address range must be in vf fb. Signed-off-by:
Zhigang Luo <zhigang.luo@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-By : Shaoyun.liu <shaoyunl@amd.com> Signed-off-by:
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Zhigang Luo authored
need to load xgmi ta for aldebaran sriov vf. Signed-off-by:
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Zhigang Luo authored
host driver programmed mmhub system aperture and fb location for vf, no need to program in guest side. Signed-off-by:
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Zhigang Luo authored
host driver programmed the gfxhub fb location for vf, no need to program in guest side. Signed-off-by:
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Zhigang Luo authored
host driver programmed fb location registers for vf, no need to check anymore. Signed-off-by:
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Xiaomeng Hou authored
Kernel test robot throws warning -> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2: warning: variable 'member_type' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47: note: uninitialized use occurs here return yellow_carp_get_smu_metrics_data(smu, member_type, value); ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2: note: variable 'member_type' is declared here MetricsMember_t member_type; ^ 1 warning generated. Fix this warning by return errno when the clk type is unsupported. Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Nirmoy Das authored
Create shadow BOs only for no-compute VM context and only for dGPU. The existing if-condition would create shadow bo for compute context on dGPU which not what we wanted. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Darren Powell authored
added doc tag "amdgpu_pp_power" with description added tags for enums pp_power_limit_level, pp_power_type added tag for function smu_get_power_limit Test: * Temporary insertion into Documentation/gpu/amdgpu.rst ------------START------------ Power Limit ----------- .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :doc: amdgpu_pp_power .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_limit_level .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_type .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c :identifiers: smu_get_power_limit -------------END------------- Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Darren Powell authored
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