- 21 Oct, 2017 40 commits
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yongqiang Sun authored
1. Fixed acquire free split pipe bug. 2. Change return value for dc_add_stream_to_ctx from bool to enum. 4. Remove redundant apply_ctx_for_surface calling 5. Unlock pipe after back end programming. Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Jerry Zuo authored
Locks are no longer needed since the drm framework takes care of correct locking. Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Jerry Zuo authored
Original code is no longer needed and tested without loop. Signed-off-by:
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Roman Li authored
Fixing loop boundaries in irq enable/disable on resume. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Charlene Liu authored
[Description] this change is in branch already. without this change, after resume, az_inst might swapped. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yue Hin Lau authored
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Charlene Liu authored
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Yongqiang Sun authored
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Shirish S authored
Currently FBC is guarded with ENABLE_FBC macro, which needs to be manually enabled in Makefile. This patch moves it to Kconfig so that there wont be any need to additional patch to be carried for enabling or disabling on every SoC. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Roman Li authored
On S3 resume the HPD6 irq source was not reenabled due to loop boundary bug. Signed-off-by:
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Tony Cheng authored
fix typo in register field. we are lucky the shift/mask is the same, no behavior change add globals to experiment with using different VM settings Signed-off-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
This reverts commit d1209512. Unfortunately these clash with our DML update from the HW guys. Rerolling this after the fact won't save us anything anymore, unfortunately so we're back to non-inline for this. Signed-off-by:
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Harry Wentland authored
This reverts commit b3fbdcec. Unfortunately these clash with our DML update from the HW guys as it's starting to get used now. Signed-off-by:
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Harry Wentland authored
This reverts commit 3e8c3108. Unfortunately these clash with our DML update from the HW guys. Will attempt to reroll them after. Signed-off-by:
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Harry Wentland authored
This reverts commit e5bcf3d8. Unfortunately these clash with our DML update from the HW guys. Will attempt to reroll them after. Signed-off-by:
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Harry Wentland authored
This reverts commit 5e0adbff. Unfortunately these clash with our DML update from the HW guys. Will attempt to reroll them after. Signed-off-by:
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Harry Wentland authored
This reverts commit d8c893b4. Unfortunately these clash with our DML update from the HW guys. Will attempt to reroll them after. Signed-off-by:
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Yue Hin Lau authored
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Charlene Liu authored
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Eric Yang authored
For verification of watermark select with SMU team, proper implementation will follow Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Wenjing Liu authored
[Description] There are many occasions we need to retrieve sink capability and notify connectivity change to os even if edid is not changed on a HPD toggle. (HDMI2.0 display needs re-enable link on every hpd, display changes other capability outside from edid need to be queried again and possibly reset the mode, etc.) In these cases we cannot keep the same sink without letting DM know. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Tony Cheng authored
in past program SMU will use all voltage headroom. RV does not if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK to improve stutter as voltage is already Signed-off-by:
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Andrew Jiang authored
A recent commit moved the backlight control code along with the register defines, but did not move the power control code. This along with remnant fields in the dce110_link_enc_registers struct made it so that the code still compiled, but any attempts to access the LVTMA_PWRSEQ_STATE register led to reading from an address of 0. This patch corrects that. Also, rename blacklight_control to edp_backlight_control (Typo fix). Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Yue Hin Lau authored
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Jerry Zuo authored
In the full update type, need to add ref_count to the newly created dc_state->stream. It made mistake to add ref_count to dc->current_state->stream which keeps adding up without release. Signed-off-by:
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Tony Cheng authored
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Tony Cheng authored
should only lower dpp clock. Signed-off-by:
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Tony Cheng authored
experimental change for testing if max line buffer result in better stutter efficiency for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of latency hiding. Signed-off-by:
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Tony Cheng authored
1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: -
Tony Cheng authored
also refactor debug option. now pipe_split_policy are dynamic = no hack around dcn_calcs. will split based on HW recommendation avoid = avoid split if we can support the config with higher voltage avoid_multi_display = allow split with single display output. force_single_disp_pipe_split force single display to pipe split to improve stutter efficiency by using DET buffers using 2 HUBP. Signed-off-by:
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Charlene Liu authored
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