- 02 Dec, 2014 40 commits
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Ben Skeggs authored
For the moment, just used to speed up vbios-only testing. Have some ideas for extending in the future. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Alexandre Courbot authored
For some reason max_vco was set to a lower value that it can support, which prevented some clock states to be applied. Fix this by setting it to the same value as downstream. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Alexandre Courbot authored
On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Signed-off-by:
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Alexandre Courbot authored
Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by:
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Alexandre Courbot authored
Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by:
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Alexandre Courbot authored
Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by:
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Alexandre Courbot authored
Pinned BOs are supposed to remain in their current location until unpinned. Display a warning for the supposedly-erroneous case where we are trying to move such objects. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Roy Spliet authored
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Roy Spliet authored
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Roy Spliet <rspliet@eclipso.eu> Signed-off-by:
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Roy Spliet authored
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Roy Spliet authored
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Roy Spliet authored
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Roy Spliet authored
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Roy Spliet authored
V2: fix whitespace errors in memx.fuc Signed-off-by:
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Roy Spliet authored
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Roy Spliet authored
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Ben Skeggs authored
No code changes. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Probably missing something here, doesn't make a lot of sense to write or+link data into a register whose offset is calculated by the same or+link info.. This is the all I've witnessed the binary driver and vbios doing so far, so it'll do. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
The binary driver has been doing this since GF119, and we've somehow gotten away with it. But, TMDS that hasn't been initialised already by the x86 vbios code is distorted without it on GM204. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Not entirely sure why this got bumped at all yet. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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