- 24 Jul, 2020 1 commit
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Jiaxun Yang authored
paravirt machine was introduced for Cavium's partial virtualization technology, however, it's host side support and QEMU support never landed in upstream. As Cavium was acquired by Marvel and they have no intention to maintain their MIPS product line, also paravirt is unlikely to be utilized by community users, it's time to retire it if nobody steps in to maintain it. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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- 21 Jul, 2020 6 commits
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Serge Semin authored
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS GIC timer and MIPS CPS CPUidle drivers. Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by:
Marc Zyngier <maz@kernel.org> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
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Serge Semin authored
CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being supported for that MIPS arch too. Signed-off-by:
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Serge Semin authored
Since having and mapping the CDMM block is platform specific, then instead of just returning a zero-address, lets make the default CDMM base address search method (mips_cdmm_phys_base()) to do something useful. For instance to find the address in a dedicated dtb-node in order to support of-based platforms by default. Signed-off-by:
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Serge Semin authored
It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Serge Semin authored
Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by:
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Serge Semin authored
It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by:
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- 16 Jul, 2020 22 commits
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Tiezhu Yang authored
In the MIPS architecture, we should clear the security-relevant flag READ_IMPLIES_EXEC in the function SET_PERSONALITY2() of the file arch/mips/include/asm/elf.h. Otherwise, with this flag set, PROT_READ implies PROT_EXEC for mmap to make memory executable that is not safe, because this condition allows an attacker to simply jump to and execute bytes that are considered to be just data [1]. In mm/mmap.c: unsigned long do_mmap(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, vm_flags_t vm_flags, unsigned long pgoff, unsigned long *populate, struct list_head *uf) { [...] if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC)) if (!(file && path_noexec(&file->f_path))) prot |= PROT_EXEC; [...] } By the way, x86 and ARM64 have done the similar thing. After commit 250c2277 ("x86_64: move kernel"), in the file arch/x86/kernel/process_64.c: void set_personality_64bit(void) { [...] current->personality &= ~READ_IMPLIES_EXEC; } After commit 48f99c8e ("arm64: Preventing READ_IMPLIES_EXEC propagation"), in the file arch/arm64/include/asm/elf.h: #define SET_PERSONALITY(ex) \ ({ \ clear_thread_flag(TIF_32BIT); \ current->personality &= ~READ_IMPLIES_EXEC; \ }) [1] https://insights.sei.cmu.edu/cert/2014/02/feeling-insecure-blame-your-parent.htmlReported-by:Juxin Gao <gaojuxin@loongson.cn> Co-developed-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Peng Fan authored
Close "fd" before the return of map_vdso() and close "out_file" in main(). Signed-off-by:
Peng Fan <fanpeng@loongson.cn> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Refresh CU1000-Neo's defconfig to support LED. Tested-by:
周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in compatible should be changed to "ingenic,x1000e". 2.Adjust the order of nodes according to the corresponding address value. 3.Drop unnecessary node in "wlan_pwrseq". 4.Add the leds node to "cu1000-neo.dts". Tested-by:
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周琰杰 (Zhou Yanjie) authored
Add a device tree and a defconfig for the Ingenic X1830 based YSH & ATIL CU Neo board. Tested-by:
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周琰杰 (Zhou Yanjie) authored
1.Add bindings for Ingenic X1830 based board, prepare for later dts. 2.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in bindings should be changed to "ingenic,x1000e", the corresponding dts file modification will be made in a patch later in this series. Tested-by:
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周琰杰 (Zhou Yanjie) authored
Support the Ingenic X1830 SoC using the code under arch/mips/jz4740. This is left unselectable in Kconfig until a X1830 based board is added in a later commit. Tested-by:
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Sunguoyun authored
sparse report build warning as follows: arch/mips/vdso/vdso-n32-image.c:13:35: incorrect type in assignment (different address spaces) @@ expected void *[usertype] vdso @@ got void [noderef] <asn:1> * @@ Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Sunguoyun <sunguoyun@loongson.cn> Signed-off-by:
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by:Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by:
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Jiaxun Yang authored
Load correct devicetree according to PRID and PCH type. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
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Jiaxun Yang authored
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and Generic Loongson64 Quad Core + LS7A boards. Signed-off-by:
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Huacai Chen authored
From previous commits, the machine names with "loongson3-" prefix have renamed to "loongson64c-" prefix in documents, but the .dts files have not been updated as well. So fix it. Signed-off-by:
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Zhi Li authored
Replace hwmon_device_register() with hwmon_device_register_with_info() to fix the following boot warning : [ 9.029924] Loongson Hwmon Enter... [ 9.106850] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). Signed-off-by:
Zhi Li <lizhi01@loongson.cn> Signed-off-by:
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Tiezhu Yang authored
Once the temperature of any CPUs is too high, it can power off immediately, no need to check the rest of CPUs, and it is better to print a log before power off, this is useful when analysis the abnormal issues. Signed-off-by:
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Tiezhu Yang authored
Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: -
Paul Cercueil authored
Add a basic default config for the RS-90 RetroMini board. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Paul Cercueil authored
The RS-90, better known as RetroMini, is a small and pocketable handheld gaming console from YLMChina. It has little more than a JZ4725B SoC, a NAND, a screen, some buttons and a speaker. Signed-off-by:
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Paul Cercueil authored
Add preliminary support for boards based on the JZ4725B SoC from Ingenic. The JZ4725B SoC is supposed to be older than the JZ4740 SoC, but its internals are much closer to what can be found on the JZ4750 and newer SoCs. It is low-power SoC with a MIPS32r1 SoC running at ~360 MHz, and no FPU. Signed-off-by:
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Paul Cercueil authored
Use an enum instead of macros to represent the various versions of the Ingenic SoCs, and add some of the SoC versions that were previously missing. Signed-off-by:
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Paul Cercueil authored
Add compatible strings for the PWM and watchdog IPs on the Ingenic JZ4725B SoC. Signed-off-by:
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Paul Cercueil authored
Add an entry to ingenic/devices.yaml for the JZ4725B-based YLM "RetroMini" RS-90. Signed-off-by:
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Paul Cercueil authored
Shenzhen Yangliming Electronic Technology Co., Ltd., abbreviated YLM or YLMChina, and known as Anbernic in the rest of the world, is a Chinese manufacturer of handheld game consoles, some of which are known to be running Linux. Signed-off-by:
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- 08 Jul, 2020 6 commits
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Wei Yongjun authored
sparse report build warning as follows: drivers/platform/mips/rs780e-acpi.c:72:6: warning: symbol 'acpi_registers_setup' was not declared. Should it be static? And function acpi_registers_setup() is not used outside of this file, so marks it static. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Huacai Chen authored
The size of ioports in the current RS780E dts file is not enough, which sometimes causes device initialize fail. So we increase the size of ISA/ LPC ioports to 0x4000, and increase the size of PCI ioports to 0x8000. Signed-off-by:
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Huacai Chen authored
Document loongson64c-4core-ls7a and loongson64g-4core-ls7a, two boards with LS7A PCH. Signed-off-by:
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Huacai Chen authored
Loongson-3A R1/R2/R3 and Loongson-3B R1/R2 use the same package naming in dts, and Loongson-3A R4 will be different. In cpu.h the classic 64bit Loongson processors are called Loongson64C (C for classic, pre Loongson- 3A R4), and the new 64bit Loongson processors are called Loongson64G (G for generic, Loongson-3A R4+). To keep consistency and make extensible, we rename the classic "loongson3" prefix to "loongson64c", and the new prefix for Loongson-3A R4+ will be "loongson64g". Signed-off-by:
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Huacai Chen authored
Adjust IRQ layout in order to use IRQ resources more efficiently, which is done by adjusting NR_IRQS and MIPS_CPU_IRQ_BASE. Before this patch: 0~15: ISA/LPC IRQs; 16~55: Dynamic IRQs; 56~63: MIPS CPU IRQs; 64~127: PCH IRQs; 128~255: Dynamic IRQs. After this patch: 0~15: ISA/LPC IRQs; 16~23: MIPS CPU IRQs; 24~87: PCH IRQs; 88~280: Dynamic IRQs. Signed-off-by:
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Huacai Chen authored
Other vendor-defined registers use the vendor name as a prefix, not an infix, so unify the naming style of CP0.Config6 bits. Suggested-by:
Maciej W. Rozycki" <macro@linux-mips.org> Signed-off-by:
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- 02 Jul, 2020 1 commit
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Thomas Bogendoerfer authored
While applying commit 9909bc43 ("dt-bindings: MIPS: Document Ingenic SoCs binding.") I've messed up by "fixing" indentation in a C style, which is wrong for yaml files. Replace tabs back to spaces. Fixes: 9909bc43 ("dt-bindings: MIPS: Document Ingenic SoCs binding.") Signed-off-by:
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- 25 Jun, 2020 3 commits
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Alexander Lobakin authored
csum_fold() in MIPS' asm/checksum.h is another source of sparse flooding when building different networking source code. The thing is that only half of __wsum <--> u32 casts inside the function is forced, which is insufficient. Add all necessary forced typecasting to stop floods and simplify actual bug hunting. Signed-off-by:
Alexander Lobakin <alobakin@pm.me> Signed-off-by:
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Alexander Lobakin authored
MIPS MMIO macros for byteswapping from/to hardware endianness are a bit tricky because they use cpu_to_le{16,32,64}() in both directions. This generates a lot of questions from sparse as __le{16,32,64} types are 'restricted' and direct cast is forbidden in order to prevent messing up the byteorder. As MMIO ops are used in almost every single driver, this leads to console flooding and complicates bug hunting. We could fix it in a more proper way, i.e. separate from device / to device byteswap macros and expand __BUILD_MEMORY_*(), but this seems redundant and will produce code duplication. Instead, just expand the existing *ioswab*() macros with forced typecasting to stop floods. Signed-off-by: -
Alexander Lobakin authored
*readq() family operates with u64 arguments, so they need 64-bit byteswaps. Correct macros for Generic MIPS and IP-32 to match other machines' implementations. Signed-off-by:
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- 22 Jun, 2020 1 commit
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Lichao Liu authored
Firstly, Loongson-2EF support ll/sc instructions, but doesn't need fix-loongson3-llsc compile option. Secondly, fix-loongson3-llsc will cause kernel startup fail at futex_init, because compiler will add 'sync' before 'll', which will affect __ex_table. futex_init will pass NULL uaddr parameter to futex_atomic_cmpxchg_inatomic. futex_atomic_cmpxchg_inatomic will access uaddr directly, which will cause page fault exception, the exception should be handled by __ex_table's nextinsn if the exception insn exsit in __ex_table. Because __ex_table is affected by compiler, the exception can not be handled, and futex_atomic_cmpxchg_inatomic will crash. Error code as below: __ex_table.insn = 1b, which is 'sync' compiled with fix-loongson3-llsc, but the actual exception instrction is ll. So, do_page_fault will not find the correct inst in __ex_table, and can not handle this exception. "1: "user_ll("%1", "%3")" \n" " bne %1, %z4, 3f \n" " .set pop \n" " move $1, %z5 \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" "2: "user_sc("$1", "%2")" \n" " beqz $1, 1b \n" "3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n" " .insn \n" " .set pop \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" " j 3b \n" " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous Signed-off-by:Lichao Liu <liulichao@loongson.cn> Reviewed-by:
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