- 03 Jan, 2014 40 commits
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Huang Shijie authored
Use devm_request_irq to simplify the code. Also remove the unused fields of structure resources{}. Signed-off-by:Huang Shijie <b32955@freescale.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
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Huang Shijie authored
Use the devm_ioremap_resource to simplify the code. [Note: as a side effect, this adds a missing call to request_memory().] Signed-off-by:
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Huang Shijie authored
The gpmi_nfc_* is the legacy name. In order to avoid the confusion, The patch renames the gpmi_nfc_* functions to gpmi_nand_*. Signed-off-by:
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Huang Shijie authored
We do not use the chip->oob_poi in the mx23_write_transcription_stamp. So remove the unused line. Signed-off-by:
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Huang Shijie authored
We do not scan the BBT after we call the gpmi_pre_bbt_scan, so it has lost the meaning of existence. This patch merges this function into gpmi_init_last, and delete it. This patch does not change any logic. Signed-off-by:
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Huang Shijie authored
The local array feature[] is in the stack. We can see the warning when we enable the CONFIG_DMA_API_DEBUG: ---------------------------------------------------------- WARNING: at lib/dma-debug.c:950 check_for_stack+0xac/0xf8() gpmi-nand 112000.gpmi-nand: DMA-API: device driver maps memory fromstack [addr=dc05be34] Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.17-16851-g2414a73 #1324 [<80014cbc>] (unwind_backtrace+0x0/0x138) from [<8001251c>] (show_stack+0x10/0x14) [<8001251c>] (show_stack+0x10/0x14) from [<8002699c>] (warn_slowpath_common+0x4c/0x68) [<8002699c>] (warn_slowpath_common+0x4c/0x68) from [<80026a4c>] (warn_slowpath_fmt+0x30/0x40) [<80026a4c>] (warn_slowpath_fmt+0x30/0x40) from [<8028e2f8>] (check_for_stack+0xac/0xf8) [<8028e2f8>] (check_for_stack+0xac/0xf8) from [<8028e438>] (debug_dma_map_sg+0xf4/0x188) [<8028e438>] (debug_dma_map_sg+0xf4/0x188) from [<803968d0>] (prepare_data_dma+0xb8/0x1a8) [<803968d0>] (prepare_data_dma+0xb8/0x1a8) from [<80397b20>] (gpmi_send_data+0x84/0xfc) [<80397b20>] (gpmi_send_data+0x84/0xfc) from [<8038c2b4>] (nand_onfi_set_features+0x50/0x74) [<8038c2b4>] (nand_onfi_set_features+0x50/0x74) from [<80397198>] (gpmi_extra_init+0x90/0x170) [<80397198>] (gpmi_extra_init+0x90/0x170) from [<8039520c>] (gpmi_nand_probe+0x2f8/0xb3c) [<8039520c>] (gpmi_nand_probe+0x2f8/0xb3c) from [<8031b974>] (platform_drv_probe+0x18/0x1c) ---------------------------------------------------------- The patch uses the kzalloc to allocate the buffer, and free it when we do not use it anymore. Signed-off-by:
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Brian Norris authored
The Armada BCH configuration in this driver uses one of the two following ECC schemes: 16-bit correction per 2048 bytes 16-bit correction per 1024 bytes These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit per 512-bytes (respectively) minimum correctability requirements of many common NAND. The current code only checks for the required strength (4-bit or 8-bit) without checking the ECC step size that is associated with that strength (and simply assumes it is 512). While that is often a safe assumption to make, let's make it explicit, since we have that information. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by:
Daniel Mack <zonque@gmail.com>
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Ezequiel Garcia authored
This commit extends the ECC correctable error detection to include ECC BCH errors. The number of BCH correctable errors can be any up to 16, and the actual value is exposed in the NDSR register. Therefore, we change some symbol names to refer to correctable or uncorrectable (instead of single-bit or double-bit as it was in the Hamming case) and while at it, cleanup the detection code slightly. Signed-off-by:
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Ezequiel Garcia authored
This commit adds write support for large pages (4 KiB, 8 KiB). Such support is implemented by issuing a multiple command sequence, transfering a set of 2 KiB chunks per transaction. The splitted command sequence requires to send the SEQIN command independently of the PAGEPROG command and therefore it's set as an execution command. Since PAGEPROG enables ECC, each 2 KiB chunk of data is written together with ECC code at a controller-fixed location within the flash page. Currently, only devices with a 4 KiB page size has been tested. Signed-off-by:
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Ezequiel Garcia authored
As preparation work to fully support large pages, this commit adds the initial infrastructure to support splitted (aka chunked) I/O operation. This commit adds support for read, and follow-up patches will add write support. When a read (aka READ0) command is issued, the driver loops issuing the same command until all the requested data is transfered, changing the 'extended' command field as needed. For instance, if the driver is required to read a 4 KiB page, using a chunk size of 2 KiB, the transaction is splitted in: 1. Monolithic read, first 2 KiB page chunk is read 2. Last naked read, second and last 2KiB page chunk is read If ECC is enabled it is calculated on each chunk transfered and added at a controller-fixed location after the data chunk that must be spare area. Signed-off-by:
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Ezequiel Garcia authored
In preparation to support multiple (aka chunked, aka splitted) page I/O, this commit adds 'data_buff_pos' and 'oob_buff_pos' fields to keep track of where the next read (or write) should be done. This will allow multiple calls to handle_data_pio() to continue the read (or write) operation. Signed-off-by:
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Ezequiel Garcia authored
This commit adds support page programming with a non-zero "column" address setting. This is important to support OOB writing, through command sequences such as: cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, ofs); write_buf(mtd, oob_buf, 6); cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); Signed-off-by:
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Ezequiel Garcia authored
To allow future support of multiple page reading/writing, move the data buffer clean out of prepare_set_command(). This is done to prevent the data buffer from being cleaned on every command preparation, when a multiple command sequence is implemented to read/write pages larger than the FIFO size (2 KiB). Signed-off-by:
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Ezequiel Garcia authored
This commit splits the prepare_command_pool() function into two stages: prepare_start_command() / prepare_set_command(). This is a preparation patch without any functionality changes, and is meant to allow support for multiple page reading/writing operations. Signed-off-by:
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Ezequiel Garcia authored
READ0 and READOOB command preparation has a falltrough to SEQIN case, where the command address is specified. This is certainly confusing and makes the code less readable with no added value. Let's remove it. Signed-off-by:
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Ezequiel Garcia authored
Let's simplify the code by first introducing a helper function to set the page address, as done by the READ0, READOOB and SEQIN commands. Signed-off-by:
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Ezequiel Garcia authored
Command buffer #3 is not properly cleared and it keeps the last set value. Fix this by clearing when a command is setup. Signed-off-by:
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Ezequiel Garcia authored
This commit adds the BCH ECC support available in NFCv2 controller. Depending on the detected required strength the respective ECC layout is selected. This commit adds an empty ECC layout, since support to access large pages is first required. Once that support is added, a proper ECC layout will be added as well. Signed-off-by:
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Ezequiel Garcia authored
Add support for flash-based bad block table using Marvell's custom in-flash bad block table layout. The support is enabled a 'flash_bbt' platform data or device tree parameter. Signed-off-by:
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Ezequiel Garcia authored
In pxa3xx_nand_sensing() instead of simply using info->is_ready after issuing a command, the correct way of checking is to wait for the device to be ready through the chip's waitfunc(). Signed-off-by:
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Ezequiel Garcia authored
The expected behavior of the waitfunc() NAND chip call is to wait for the device to be READY (this is a standard chip line). However, the current implementation does almost nothing, which opens the possibility of issuing a command to a non-ready device. Fix this by adding a new completion to wait for the ready event to arrive. Signed-off-by:
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Ezequiel Garcia authored
Add a comment clarifying the use of pxa3xx_set_datasize() which is only applicable on data read/write commands (i.e. commands with a data cycle, such as READID, READ0, STATUS, etc.) Signed-off-by:
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Ezequiel Garcia authored
There's no need to privately store the device page size as it's available in mtd structure field mtd->writesize. Also, this removes the hardcoded page size value, leaving the auto-detected value only. Signed-off-by:
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Ezequiel Garcia authored
Introduce a fifo_size field to represent the size of the controller's FIFO buffer, and use it to distinguish that size from the amount of data bytes to be read from the FIFO. This is important to support devices with pages larger than the controller's internal FIFO, that need to read the pages in FIFO-sized chunks. In particular, the current code is at least confusing, for it mixes all the different sizes involved: FIFO size, page size and data size. This commit starts the cleaning by removing the info->page_size field that is not currently used. The host->page_size field should also be removed and use always mtd->writesize instead. Follow up commits will clean this up. Signed-off-by:
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Ezequiel Garcia authored
Whenever possible, it's always better to use the generic chip->cmdfunc instead of the internal pxa3xx_nand_cmdfunc(). In this particular case, this will allow to have multiple cmdfunc() implementations for different SoC variants. Reviewed-by:
Huang Shijie <shijie8@gmail.com> Signed-off-by:
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Ezequiel Garcia authored
In order to customize early settings depending on the detected SoC variant, move the detection to be before the nand_chip struct filling. In a follow-up patch, this change is needed to detect the variant *before* the call to alloc_nand_resource(), which allows to set a different cmdfunc() for each variant. Signed-off-by:
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Ezequiel Garcia authored
As per the ecc.read_page() prototype, we must return the maximum number of bitflips that were corrected on any one region covering an ecc step. Signed-off-by:
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Ezequiel Garcia authored
The current driver doesn't support sub-page writing, so report that to the NAND core. Signed-off-by:
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Ezequiel Garcia authored
Since we have now support for the NFCv2 controller found on Armada 370/XP platforms. Signed-off-by:
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Ezequiel Garcia authored
Given there's no public specification to this date, and in order to capture some important details and singularities about the controller let's document them once and for good. Cc: linux-doc@vger.kernel.org Signed-off-by:
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Ezequiel Garcia authored
Since the driver supports the new compatible string, the binding documentation must be updated to reflect it. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Signed-off-by:
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Geert Uytterhoeven authored
This allows to drop a few casts. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Geert Uytterhoeven authored
mtd_info.name is "const char *" Signed-off-by:
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Geert Uytterhoeven authored
device_driver.name is "const char *" Signed-off-by:
Olof Johansson <olof@lixom.net> Cc: linux-mtd@lists.infradead.org Signed-off-by:
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Geert Uytterhoeven authored
map_info.name is "const char *" Signed-off-by:
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Fabio Estevam authored
Fix the following checkpatch warnings: WARNING: line over 80 characters #268: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:268: + * consecutive reboots. The latter case has not been seen on the MX23 yet, WARNING: space prohibited before semicolon #356: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:356: + (target.tRHOH_in_ns >= 0) ; WARNING: space prohibited before semicolon #1006: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:1006: + BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ; Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
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Fabio Estevam authored
Using devm_clk_get() can make the code smaller and cleaner. Signed-off-by:
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Huang Shijie authored
In default way, we use the ecc_strength/ecc_step size calculated by ourselves and use all the OOB area. This patch adds a new property : "fsl,use-minimum-ecc" If we enable it, we will firstly try to use the datasheet's minimum required ECC provided by the MTD layer (the ecc_strength_ds/ecc_step_ds fields in the nand_chip{}). So we may have free space in the OOB area by using the minimum ECC, and we may support JFFS2 with some SLC NANDs, such as Micron's SLC NAND. If we fail to use the minimum ECC, we will use the legacy method to calculate the ecc_strength and ecc_step size. Signed-off-by: -
Ezequiel Garcia authored
This option does not need to depend in MTD_NAND, for it's enclosed under it. Also, it's wrong to make it depend in ARCH_OMAP3 only since the controller is used in a wider range of SoCs. Instead, just leave the dependency on the OMAP2 driver option. Signed-off-by:
Pekon Gupta <pekon@ti.com> Signed-off-by:
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Sourav Poddar authored
Some flash also support quad read mode. Adding support for quad read mode in m25p80 for Spansion and Macronix flash. [Tweaked by Brian] With this patch, quad-read support will override fast-read and normal-read, if the SPI controller and flash chip both support it. Signed-off-by:
Sourav Poddar <sourav.poddar@ti.com> Tested-by:
Marek Vasut <marex@denx.de> Signed-off-by:
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