1. 23 Aug, 2022 1 commit
    • Conor Dooley's avatar
      riscv: dts: microchip: mpfs: fix incorrect pcie child node name · 3f67e699
      Conor Dooley authored
      Recent versions of dt-schema complain about the PCIe controller's child
      node name:
      arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
                  From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
      Make the dts match the correct property name in the dts.
      
      Fixes: 528a5b1f ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
      Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      3f67e699
  2. 17 Aug, 2022 1 commit
    • Heinrich Schuchardt's avatar
      riscv: dts: microchip: correct L2 cache interrupts · 34fc9cc3
      Heinrich Schuchardt authored
      The "PolarFire SoC MSS Technical Reference Manual" documents the
      following PLIC interrupts:
      
      1 - L2 Cache Controller Signals when a metadata correction event occurs
      2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs
      3 - L2 Cache Controller Signals when a data correction event occurs
      4 - L2 Cache Controller Signals when an uncorrectable data event occurs
      
      This differs from the SiFive FU540 which only has three L2 cache related
      interrupts.
      
      The sequence in the device tree is defined by an enum:
      
          enum {
                  DIR_CORR = 0,
                  DATA_CORR,
                  DATA_UNCORR,
                  DIR_UNCORR,
          };
      
      So the correct sequence of the L2 cache interrupts is
      
          interrupts = <1>, <3>, <4>, <2>;
      
      [Conor]
      This manifests as an unusable system if the l2-cache driver is enabled,
      as the wrong interrupt gets cleared & the handler prints errors to the
      console ad infinitum.
      
      Fixes: 0fa6107e ("RISC-V: Initial DTS for Microchip ICICLE board")
      CC: stable@vger.kernel.org # 5.15: e35b07a7: riscv: dts: microchip: mpfs: Group tuples in interrupt properties
      Signed-off-by: default avatarHeinrich Schuchardt <heinrich.schuchardt@canonical.com>
      Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      34fc9cc3
  3. 13 Aug, 2022 3 commits
    • Linus Torvalds's avatar
      Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux · 69dac8e4
      Linus Torvalds authored
      Pull more RISC-V updates from Palmer Dabbelt:
       "There's still a handful of new features in here, but there are a lot
        of fixes/cleanups as well:
      
         - Support for the Zicbom extension for explicit cache-block
           management, along with the necessary bits to make the non-standard
           cache management ops on the Allwinner D1 function
      
         - Support for the Zihintpause extension, which codifies a go-slow
           instruction used for cpu_relax()
      
         - Support for the Sstc extension for supervisor-mode timer/counter
           management
      
         - Many device tree fixes and cleanups, including a large set for the
           Canaan device trees
      
         - A handful of fixes and cleanups for the PMU driver"
      
      * tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (43 commits)
        dt-bindings: gpio: sifive: add gpio-line-names
        wireguard: selftests: set CONFIG_NONPORTABLE on riscv32
        RISC-V: KVM: Support sstc extension
        RISC-V: Improve SBI definitions
        RISC-V: Move counter info definition to sbi header file
        RISC-V: Fix SBI PMU calls for RV32
        RISC-V: Update user page mapping only once during start
        RISC-V: Fix counter restart during overflow for RV32
        RISC-V: Prefer sstc extension if available
        RISC-V: Enable sstc extension parsing from DT
        RISC-V: Add SSTC extension CSR details
        riscv:uprobe fix SR_SPIE set/clear handling
        dt-bindings: riscv: fix SiFive l2-cache's cache-sets
        riscv: ensure cpu_ops_sbi is declared
        RISC-V: cpu_ops_spinwait.c should include head.h
        RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>
        riscv: dts: starfive: correct number of external interrupts
        riscv: dts: sifive unmatched: Add PWM controlled LEDs
        riscv/purgatory: Omit use of bin2c
        riscv/purgatory: hard-code obj-y in Makefile
        ...
      69dac8e4
    • Linus Torvalds's avatar
      Merge tag 'devicetree-fixes-for-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux · 6c833c05
      Linus Torvalds authored
      Pull devicetree fixes from Rob Herring:
      
       - Fix schema warnings in qcom,ipq6018-pinctrl and sdhci-msm
      
       - Convert Qualcomm SPMI PMIC to DT schema
      
       - Make secure interrupt optional for arm,mhu
      
       - Fix google,cros-ec-typec binding allowed properties
      
       - Update a bunch of bouncing email addresses
      
      * tag 'devicetree-fixes-for-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
        dt-bindings: chrome: google,cros-ec-typec: restrict allowed properties
        dt-bindings: Drop Dan Murphy and Ricardo Rivera-Matos
        dt-bindings: Drop Robert Jones
        dt-bindings: Drop Beniamin Bia and Stefan Popa
        dt-bindings: iio: Drop Bogdan Pricop
        dt-bindings: iio: Drop Joachim Eastwood
        dt-bindings: mailbox: arm,mhu: Make secure interrupt optional
        dt-bindings: pinctrl: qcom,ipq6018: Fix example 'gpio-ranges' size
        dt-bindings: Drop DT_MK_SCHEMA_FLAGS conditional selecting schema files
        dt-bindings: mfd: convert to yaml Qualcomm SPMI PMIC
        dt-bindings: mmc: sdhci-msm: Fix 'operating-points-v2 was unexpected' issue
        dt-bindings: display: simple-framebuffer: Drop Bartlomiej Zolnierkiewicz
      6c833c05
    • Linus Torvalds's avatar
      Merge tag 'rtc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux · 3d076fec
      Linus Torvalds authored
      Pull RTC updates from Alexandre Belloni:
       "New drivers:
         - Microchip PolarFire
         - Nuvoton NCT3018Y
         - TI K3 RTC
      
        Subsystem:
         - Replace flush_scheduled_work() with flush_work()
         - Remove deprecated ida_simple_get()/ida_simple_remove() calls
      
        Drivers:
         - use simple i2c probe where possible
         - sun6i: add R329 support
         - zynqmp: add calibration support
         - vr41xx: remove unused driver"
      
      * tag 'rtc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (31 commits)
        rtc: spear: set range max
        rtc: rtc-cmos: Do not check ACPI_FADT_LOW_POWER_S0
        rtc: zynqmp: initialize fract_tick
        rtc: Add NCT3018Y real time clock driver
        dt-bindings: rtc: nuvoton: add NCT3018Y Real Time Clock
        dt-bindings: rtc: nxp,pcf85063: Convert to DT schema
        dt-bindings: rtc: microcrystal,rv3032: Add missing type to 'trickle-voltage-millivolt'
        rtc: rx8025: fix 12/24 hour mode detection on RX-8035
        rtc: cros-ec: Only warn once in .remove() about notifier_chain problems
        rtc: vr41xx: remove driver
        rtc: mpfs: remove 'pending' variable from mpfs_rtc_wakeup_irq_handler()
        rtc: rv8803: fix missing unlock on error in rv8803_set_time()
        rtc: zynqmp: Add calibration set and get support
        rtc: zynqmp: Updated calibration value
        dt-bindings: rtc: zynqmp: Add clock information
        rtc: sun6i: add support for R329 RTC
        rtc: Directly use ida_alloc()/free()
        rtc: Introduce ti-k3-rtc
        dt-bindings: rtc: Add TI K3 RTC description
        dt-bindings: rtc: qcom-pm8xxx-rtc: Update the maintainers section
        ...
      3d076fec
  4. 12 Aug, 2022 33 commits
  5. 11 Aug, 2022 2 commits