Merge tag 'intel-pinctrl-v5.12-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.12-1

* Enable pin control on Intel Alder Lake-P
* Traverse through capabilities, convert them to features for the future use

The following is an automated git shortlog grouped by driver:

intel:
 -  Convert capability list to features
 -  Drop unnecessary check for predefined features
 -  Split intel_pinctrl_add_padgroups() for better maintenance

tigerlake:
 -  Add Alder Lake-P ACPI ID

Linux 5.11-rc2

Add the function selector to the pinmux-functions debugfs output. This
is an integer which is the index into the pinmux function tree.  It will
make it easier to correlate function name to function selector without
having to count the lines in the output.

Example output of "pinmux-functions":

function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ]
function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ]
function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ]
function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ]
function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ]
function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ]
function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ]
function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ]
function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ]
function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ]
function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ]

Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Robert Nelson <robertcnelson@beagleboard.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20210123202212.528046-1-drew@beagleboard.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This patch converts spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt. This can avoid BUG() assertion when
irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex
which is preemptible when we apply preempt-rt patches.

According to "Documentation/driver-api/gpio/driver.rst",

"Realtime considerations: a realtime compliant GPIO driver should not
use spinlock_t or any sleepable APIs (like PM runtime) as part of its
irqchip implementation.

- spinlock_t should be replaced with raw_spinlock_t.[1]
"

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Document that #pinctrl-cells can be 1 or 2 for pinctrl-single,pins

Fixes: 27c90e5e ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2")
Reported-by: Emmanuel Vadot <manu@bidouilliste.com>
Link: https://lore.kernel.org/linux-gpio/20210115190201.9273b637a7f967e7e55bc740@bidouilliste.com/
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210120050342.320704-1-drew@beagleboard.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64
platforms. So let's add the correct platform dependency to avoid them
being selected on the other.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210121062547.27173-1-manivannan.sadhasivam@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

A new SoC, a new compatible string.
Also we were too miserly with just allowing seven interrupt banks.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210118020848.11721-4-andre.przywara@arm.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

- Add otg function and otg-vbus group.

- Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special
  groups. Change the lcd-24bit group so that it only selects the pins
  that aren't in the lcd-18bit and lcd-generic groups (which breaks
  Device Tree in theory, but there is none out there for any JZ4760
  based board, yet). Remove the lcd-no-pins group which is just useless.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

yamllint warns:
./Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml
  102:10  error   wrong indentation: expected 10 but found 9 (indentation)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20210116015350.3501927-1-j.neuschaefer@gmx.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Fix the follow coccicheck warnings:

./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING:
Comparison to bool.
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
Link: https://lore.kernel.org/r/1610705349-24310-1-git-send-email-abaci-bugfix@linux.alibaba.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves
about 14 KiB, by allowing the compiler to garbage-collect all the
functions and tables that correspond to SoCs that were disabled in the
config.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

IF_ENABLED(CONFIG_FOO, ptr) evaluates to (ptr) if CONFIG_FOO is set to 'y'
or 'm', NULL otherwise. The (ptr) argument must be a pointer.

The IF_ENABLED() macro can be very useful to help GCC drop dead code.

For instance, consider the following:

    #ifdef CONFIG_FOO_SUSPEND
    static int foo_suspend(struct device *dev)
    {
       ...
    }
    #endif

    static struct pm_ops foo_ops = {
	#ifdef CONFIG_FOO_SUSPEND
        .suspend = foo_suspend,
	#endif
    };

While this works, the foo_suspend() macro is compiled conditionally,
only when CONFIG_FOO_SUSPEND is set. This is problematic, as there could
be a build bug in this function, we wouldn't have a way to know unless
the config option is set.

An alternative is to declare foo_suspend() always, but mark it as maybe
unused:

    static int __maybe_unused foo_suspend(struct device *dev)
    {
       ...
    }

    static struct pm_ops foo_ops = {
	#ifdef CONFIG_FOO_SUSPEND
        .suspend = foo_suspend,
	#endif
    };

Again, this works, but the __maybe_unused attribute is required to
instruct the compiler that the function may not be referenced anywhere,
and is safe to remove without making a fuss about it. This makes the
programmer responsible for tagging the functions that can be
garbage-collected.

With this patch, it is now possible to write the following:

    static int foo_suspend(struct device *dev)
    {
       ...
    }

    static struct pm_ops foo_ops = {
        .suspend = IF_ENABLED(CONFIG_FOO_SUSPEND, foo_suspend),
    };

The foo_suspend() function will now be automatically dropped by the
compiler, and it does not require any specific attribute.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20201213235447.138271-1-paul@crapouillou.netSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'renesas-pinctrl-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.12

  - Restrict debug runtime-checks to Renesas platforms,
  - Initial support for the R-Car V3U SoC.

Fix the following coccicheck warning:
./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to
bool
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com>
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Link: https://lore.kernel.org/r/1610440080-68600-1-git-send-email-abaci-bugfix@linux.alibaba.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Kernel test robot throws below warning ->

smatch warnings:
drivers/pinctrl/ti/pinctrl-ti-iodelay.c:708
ti_iodelay_pinconf_group_dbg_show() warn: inconsistent indenting

Fixed the inconsistent indenting.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com>
Link: https://lore.kernel.org/r/1610394585-4296-1-git-send-email-jrdr.linux@gmail.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
driver.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds CANFD 0-7 and CANFD clock pinmux support for the
R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and
PTP pins for the R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U)
SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the
R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.

Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.

To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.euSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Document PFC support for the R-Car V3U (R8A779A0) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165912.30876-7-uli+renesas@fpond.eu
[geert: increase reg maxItems to 10]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin
control driver runs sanity checks against the pin control tables.  This
may cause lots of output on the console, and can be annoying in ARM
multi-platform kernels.  Fix this by only running the checks when
running on SuperH, or on a DT platform supported by the Renesas pin
controller driver.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be