- 05 Dec, 2023 8 commits
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Jai Luthra authored
RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM62A through the 22-pin CSI-RX connector. Same overlay can be used across SK-AM62* boards that have a 15/22-pin FFC connector, so we name it with the k3-am62x- prefix. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-8-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
Enable I2C-2 as it is used to control CSI based sensors. Also enable IO-EXP-2 as it controls the mux between different CSI-2 connectors. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-7-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
Three different OV5640 modules are supported using the 15-pin FFC connector on SK-AM62: - Digilent PCam 5C - ALINX AN5641 - TEVI-OV5640-*-RPI The Digilent and ALINX modules supply a 12Mhz XCLK to the sensor, while the TEVI module supplies a 24Mhz XCLK, thus requiring a separate overlay. These overlays can be used on other boards of the SK-AM62* family that have a 15/22-pin FFC connector, so we name the overlays with the prefix k3-am62x-. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-6-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
CSI cameras are controlled using I2C, on SK-AM62 and derivative boards this is routed to I2C-2, so enable that bus. Specific sensor connected to this bus will be described in the DT overlay for each sensor. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-5-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
Three different OV5640 modules are supported using the FFC connector on BeaglePlay: - Digilent PCam 5C - ALINX AN5641 - TEVI-OV5640-*-RPI The Digilent and ALINX modules supply a 12Mhz XCLK to the sensor, while the TEVI module supplies a 24Mhz XCLK, thus requiring a separate overlay. Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-4-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
Add nodes for Cadence DPHY, CSI2RX and TI's pixel-grabbing wrapper. AM62A uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-3-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jai Luthra authored
The CSI2RX subsystem can be used to capture video frames from CSI-2 cameras. Add nodes for the CSI core, SHIM layer, and the DPHY. Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231201-csi_dts-v3-2-9f06f31080fe@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
The AM652 is basically a AM654 but with 2 cores instead of 4. Add a DTSI file for AM652 matching AM654 except this core difference. This removes the need to remove the extra cores from AM654 manually in DT files for boards that use the AM652 variant. Do that for the IOT2050 boards here. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20231205162358.23904-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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- 04 Dec, 2023 12 commits
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Andrew Davis authored
The main_uart0 may not always be the console, but it will always be the UART0 in MAIN domain. Name the pinmux node to match. This makes it consistent with all other TI SoC based boards. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231127193602.151499-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Aradhya Bhatia authored
The Hot Plug Detect (HPD) signal for the HDMI display travels from the on-board HDMI connector, through the IO Expander 1, and finally to the main_gpio1 GPIO 23, of the SoC. Add interrupt information for the IO Expander 1 (exp1) along with the relevant pinmux. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231108191652.1118155-1-a-bhatia1@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Parth Pancholi authored
Enable UART2 for AM62 based SOM's Verdin carrier boards Dahlia, Development and Yavia. Earlier Verdin UART2 was reserved by R5 DM firmware which can be now configured using boardcfg during U-boot compilation. In a default config, no one writes to this UART. Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20231121160436.1032364-1-parth105105@gmail.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Ronald Wahl authored
On the AM62 platform we have no single 1:1 relation regarding index of gpio and pin controller. Actually there are some linear ranges with small holes inbetween. These ranges can be represented with the gpio-ranges device tree property. They have been extracted manually from the AM62x datasheet (Table 6-1. Pin Attributes). Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com> Link: https://lore.kernel.org/r/20231127112657.2692103-1-rwahl@gmx.deSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
This matches the binding for this register region which fixes a couple DTS check warnings. While here trim the leading 0s from the "reg" definition. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20231117141433.9461-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-2-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-3-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-5-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
Like in other K3 SoCs the chipid register is inside the wakeup configuration space. Move the chipid node under a new bus to better represent this topology and match other similar SoCs. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117140910.8747-4-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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- 01 Dec, 2023 13 commits
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Siddharth Vadapalli authored
Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Link: https://lore.kernel.org/r/20231115085913.3585740-1-s-vadapalli@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jan Kiszka authored
Add the required nodes to enable ICSSG SR2.0 based prueth networking. As the driver still needs to be extended for SR1.0 support, keep related nodes disabled on PG1 devices. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/565d31a5fd29c4dd0cf28e347049a1247a6e446c.1699087938.git.jan.kiszka@siemens.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Su Bao Cheng authored
Make the m.2 power control pin also available on miniPCIE variants. This can fix some miniPCIE card hang issue, by forcing a power on reset during boot. Signed-off-by: Baocheng Su <baocheng.su@siemens.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/8b2f8c1698421b8d0694eb337ad7ea2320d76aa6.1699087938.git.jan.kiszka@siemens.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Benedikt Niedermayr authored
Add multiple device tree nodes in order to support runtime pinmuxing via debugfs. All nodes are added to the pinctrl device node, since they are now belonging to multiple interfaces now. Note: Pinconf is also handled by debugfs-pinmux. This is possible since pinconf and pinmux accessing the same 32-Bit register and setting the function mask to 32-Bit allows writes to the whole register. Signed-off-by: Benedikt Niedermayr <benedikt.niedermayr@siemens.com> [Jan: fix node name style] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/3f90f3e521758622aa9b10f030cf0de1e68e77a4.1699087938.git.jan.kiszka@siemens.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jan Kiszka authored
In fact, this was never used by the final device, only dates back to first prototypes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/6131d44e0505ca3efbb9039e5f2b637a3e139312.1699087938.git.jan.kiszka@siemens.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Jan Kiszka authored
Lost while dropping them from the common dtsi. Fixes: ffc449e0 ("arm64: dts: ti: k3-am65: Drop aliases") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/1edbc1b56ed4ff2256d7afb7db3cab4b3a423692.1699087938.git.jan.kiszka@siemens.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Vignesh Raghavendra authored
These are typically under MCU Firmware usage. Hence mark them reserved. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20231110132508.3137454-3-vigneshr@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Vignesh Raghavendra authored
These are typically under MCU Firmware usage. Hence mark them reserved. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20231110132508.3137454-2-vigneshr@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Vignesh Raghavendra authored
Similar to MCU GPIO, mark the MCU GPIO router also as reserved for MCU domain firmware usage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20231110132508.3137454-1-vigneshr@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Andrew Davis authored
The node name has @4140 but the reg is at 4130, fix this here. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117162059.88633-1-afd@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Tomi Valkeinen authored
DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING in the DT file, but the TRM says it is level triggered. For some reason triggering on rising edge results in double the amount of expected interrupts, e.g. for normal page flipping test the number of interrupts per second is 2 * fps. It is as if the IRQ triggers on both edges. There are no other side effects to this issue than slightly increased CPU & power consumption due to the extra interrupt. Switching to IRQ_TYPE_LEVEL_HIGH is correct and fixes the issue, so let's do that. Fixes: fc539b90 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20231106-am65-dss-clk-edge-v1-1-4a959fec0e1e@ideasonboard.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Nitin Yadav authored
Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according to AM62A7 datasheet[0]. [0] https://www.ti.com/lit/gpn/am62a3 Section: 6.3.10 GPIO (Page No. 52-55) Fixes: 5fc6b1b6 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Nitin Yadav <n-yadav@ti.com> Link: https://lore.kernel.org/r/20231027065930.1187405-1-n-yadav@ti.comSigned-off-by: Nishanth Menon <nm@ti.com>
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231124095000.58487-2-krzysztof.kozlowski@linaro.orgSigned-off-by: Nishanth Menon <nm@ti.com>
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- 13 Nov, 2023 1 commit
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Linus Torvalds authored
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- 12 Nov, 2023 5 commits
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Miri Korenblit authored
The commands should be sorted inside the group definition. Fix the ordering so we won't get following warning: WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)) Link: https://lore.kernel.org/regressions/2fa930bb-54dd-4942-a88d-05a47c8e9731@gmail.com/ Link: https://lore.kernel.org/linux-wireless/CAHk-=wix6kqQ5vHZXjOPpZBfM7mMm9bBZxi2Jh7XnaKCqVf94w@mail.gmail.com/ Fixes: b6e3d1ba ("wifi: iwlwifi: mvm: implement new firmware API for statistics") Tested-by: Niklāvs Koļesņikovs <pinkflames.linux@gmail.com> Tested-by: Damian Tometzki <damian@riscv-rocks.de> Acked-by: Kalle Valo <kvalo@kernel.org> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
Merge tag 'parisc-for-6.7-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux Pull parisc architecture fixes from Helge Deller: - Include the upper 5 address bits when inserting TLB entries on a 64-bit kernel. On physical machines those are ignored, but in qemu it's nice to have them included and to be correct. - Stop the 64-bit kernel and show a warning if someone tries to boot on a machine with a 32-bit CPU - Fix a "no previous prototype" warning in parport-gsc * tag 'parisc-for-6.7-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Prevent booting 64-bit kernels on PA1.x machines parport: gsc: mark init function static parisc/pgtable: Do not drop upper 5 address bits of physical address
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Linus Torvalds authored
Merge tag 'loongarch-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch updates from Huacai Chen: - support PREEMPT_DYNAMIC with static keys - relax memory ordering for atomic operations - support BPF CPU v4 instructions for LoongArch - some build and runtime warning fixes * tag 'loongarch-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: selftests/bpf: Enable cpu v4 tests for LoongArch LoongArch: BPF: Support signed mod instructions LoongArch: BPF: Support signed div instructions LoongArch: BPF: Support 32-bit offset jmp instructions LoongArch: BPF: Support unconditional bswap instructions LoongArch: BPF: Support sign-extension mov instructions LoongArch: BPF: Support sign-extension load instructions LoongArch: Add more instruction opcodes and emit_* helpers LoongArch/smp: Call rcutree_report_cpu_starting() earlier LoongArch: Relax memory ordering for atomic operations LoongArch: Mark __percpu functions as always inline LoongArch: Disable module from accessing external data directly LoongArch: Support PREEMPT_DYNAMIC with static keys
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git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds authored
Pull powerpc fixes from Michael Ellerman: - Finish a refactor of pgprot_framebuffer() which dependend on some changes that were merged via the drm tree - Fix some kernel-doc warnings to quieten the bots Thanks to Nathan Lynch and Thomas Zimmermann. * tag 'powerpc-6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/rtas: Fix ppc_rtas_rmo_buf_show() kernel-doc powerpc/pseries/rtas-work-area: Fix rtas_work_area_reserve_arena() kernel-doc powerpc/fb: Call internal __phys_mem_access_prot() in fbdev code powerpc: Remove file parameter from phys_mem_access_prot() powerpc/machdep: Remove trailing whitespaces
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git://git.samba.org/sfrench/cifs-2.6Linus Torvalds authored
Pull smb client fixes from Steve French: - ctime caching fix (for setxattr) - encryption fix - DNS resolver mount fix - debugging improvements - multichannel fixes including cases where server stops or starts supporting multichannel after mount - reconnect fix - minor cleanups * tag '6.7-rc-smb3-client-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6: cifs: update internal module version number for cifs.ko cifs: handle when server stops supporting multichannel cifs: handle when server starts supporting multichannel Missing field not being returned in ioctl CIFS_IOC_GET_MNT_INFO smb3: allow dumping session and tcon id to improve stats analysis and debugging smb: client: fix mount when dns_resolver key is not available smb3: fix caching of ctime on setxattr smb3: minor cleanup of session handling code cifs: reconnect work should have reference on server struct cifs: do not pass cifs_sb when trying to add channels cifs: account for primary channel in the interface list cifs: distribute channels across interfaces based on speed cifs: handle cases where a channel is closed smb3: more minor cleanups for session handling routines smb3: minor RDMA cleanup cifs: Fix encryption of cleared, but unset rq_iter data buffers
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- 11 Nov, 2023 1 commit
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Linus Torvalds authored
Merge tag 'probes-fixes-v6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace Pull probes fixes from Masami Hiramatsu: - Documentation update: Add a note about argument and return value fetching is the best effort because it depends on the type. - objpool: Fix to make internal global variables static in test_objpool.c. - kprobes: Unify kprobes_exceptions_nofify() prototypes. There are the same prototypes in asm/kprobes.h for some architectures, but some of them are missing the prototype and it causes a warning. So move the prototype into linux/kprobes.h. - tracing: Fix to check the tracepoint event and return event at parsing stage. The tracepoint event doesn't support %return but if $retval exists, it will be converted to %return silently. This finds that case and rejects it. - tracing: Fix the order of the descriptions about the parameters of __kprobe_event_gen_cmd_start() to be consistent with the argument list of the function. * tag 'probes-fixes-v6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace: tracing/kprobes: Fix the order of argument descriptions tracing: fprobe-event: Fix to check tracepoint event and return kprobes: unify kprobes_exceptions_nofify() prototypes lib: test_objpool: make global variables static Documentation: tracing: Add a note about argument and retval access
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