- 27 Jun, 2018 1 commit
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José Roberto de Souza authored
It was only used in VLV/CHV so after the removal of the PSR support for those platforms it is not necessary any more. v7: Rebased Reviewed-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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- 26 Jun, 2018 4 commits
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Dhinakaran Pandiyan authored
Depending whether PSR1 or PSR2 was configured, we print a warning if the corresponding control mmio indicated PSR was erroneously enabled. As Chris pointed out, it makes more sense to check for both the mmio's since we expect neither PSR1 nor PSR2 to be enabled when psr_activate() is called. v2: Read PSR2 control register only on supported platforms (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180626090522.17682-1-dhinakaran.pandiyan@intel.com
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Dhinakaran Pandiyan authored
Commit 5422b37c ("drm/i915/psr: Kill delays when activating psr back.") switched from delayed work to the plain variant and while doing so removed the check for work_busy() before scheduling a PSR activation. This appears to cause consecutive executions of psr_activate() in this scenario - after a worker picks up the PSR work item for execution and before the work function can acquire the PSR mutex, a psr_flush() can get hold of the mutex and schedule another PSR work. Without a psr_exit() between the two psr_activate() calls, warning messages get printed. Further, since we drop the mutex in the midst of psr_work() to wait for PSR to idle, another work item can also get scheduled. Fix this by returning if PSR was already active. Fixes: 5422b37c ("drm/i915/psr: Kill delays when activating psr back.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106948 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Rodrigo Vivi authored
At some point we introduced the function pointers on PSR code to help with VLV/CHV separation logic because it had a different HW implementation from PSR. Since all converged to HSW PSR and we dropped the VLV/CHV support, let's also kill the useless function pointers and leave the code cleaner. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180626052536.15137-1-rodrigo.vivi@intel.com
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Imre Deak authored
So far we got an AUX power domain reference only for the duration of DP AUX transfers. However, the following suggests that we also need these for main link functionality: - The specification doesn't state whether it's needed or not for main link functionality, but suggests that these power wells need to be enabled already during display core initialization (Sequences to Initialize Display). - For PSR we need to keep the AUX power well enabled. - On ICL combo PHY ports (non-TC) the AUX power well is needed for link training too: while the port is enabled with a DP link training test pattern trying to toggle the AUX power well will time out. - On ICL MG PHY ports (TC) the AUX power well is needed also for main link functionality (both in DP and HDMI modes). - Windows enables these power wells both for main and AUX lane functionality. Based on the above take an AUX power reference for main link functionality too. This makes a difference only on GEN10+ (GLK+) platforms, where we have separate port specific AUX power wells. For PSR we still need to distinguish between port A and the other ports, since on port A DC states must stay enabled for main link functionality, but DC states must be disabled for driver initiated AUX transfers. So re-use the corresponding helper from intel_psr.c. Since we take now a reference for main link functionality on all DP ports we can forgo taking the separate power ref for PSR functionality. v2: - Make sure DC states stay enabled when taking the ref on port A. (Ville) v3: (Ville) - Fix comment about logic for encoders without a crtc state and add FIXME note for a simplification to avoid calling get_power_domains in such cases. - Use intel_crtc_has_dp_encoder() instead !intel_crtc_has_type(HDMI). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> [Clarified code comments in intel_ddi_main_link_aux_domain() and intel_ddi_get_power_domains() (Imre)] Reviewed-by:
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- 25 Jun, 2018 3 commits
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Chris Wilson authored
Due to how we only release the pining on the context state on retirement and never track activity on the context vma itself, the object can never be active at the point of release. Replace the conditional transfer of ownership onto an active-reference with an assert that the object is idle. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180625100604.22598-2-chris@chris-wilson.co.uk
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Chris Wilson authored
As we may cancel the ce->state allocation during context pinning (but crucially after we mark ce as operational), that means we may be asked to destroy a nonexistent ce->state. Given the choice in handing a complex error path on pinning, and just ignoring the lack of state in destroy, choice the latter for simplicity. Reported-by:
Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
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Chris Wilson authored
If we avoid cleaning up the old state immediately in intel_atomic_commit_tail() and defer it to a second task, we can avoid taking heavily contended locks when the caller is ready to procede. Subsequent modesets will wait for the cleanup operation (either directly via the ordered modeset wq or indirectly through the atomic helperr) which keeps the number of inflight cleanup tasks in check. As an example, during reset an immediate modeset is performed to disable the displays before the HW is reset, which must avoid struct_mutex to avoid recursion. Moving the cleanup to a separate task, defers acquiring the struct_mutex to after the GPU is running again, allowing it to complete. Even in a few patches time (optimist!) when we no longer require struct_mutex to unpin the framebuffers, it will still be good practice to minimise the number of contention points along reset. The mutex dependency still exists (as one modeset flushes the other), but in the short term it resolves the deadlock for simple reset cases. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101600Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by:
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- 22 Jun, 2018 1 commit
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Anusha Srivatsa authored
In the guc_ctl_debug_flags, the ads struct is programmed only when USES_GUC_SUBMISSION is satisfied. But, this has to be programmed for all suspend/resume cases. Remove the condition and program the ads struct for both huc loading and guc submission. This issue was noticed when CI threw errors for enable_guc=2 (load huc; disable submission) v2: - Change commit title. - Correct the shifts. (Daniele) Credits to: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Spotswood <john.a.spotswood@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
John Spotswood <john.a.spotswood@intel.com> Signed-off-by:
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- 21 Jun, 2018 6 commits
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Vandita Kulkarni authored
Alpha blending with alpha 0 and 0xff passes through alpha math and rounding logic causing differences compared to fully transparent or opaque plane,resulting in CRC mismatch. This WA on icl and above enables hardware to bypass alpha math and rounding for per pixel alpha values of 00 and 0xff v2: Fix patchwork checkpatch warnings. Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
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Imre Deak authored
Some MG PLL registers have fields that need to be preserved at their HW default or BIOS programmed values. So make sure we preserve them. v2: - Add comment to icl_mg_pll_write() explaining the need for register masks. (Vandita) - Fix patchwork checkpatch warning. v3: - Rebase on drm-tip. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by:
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Imre Deak authored
Atm we're zeroing out fields in MG_PLL_BIAS and MG_PLL_TDC_COLDST_BIAS if refclk is 38.4MHz, whereas the spec tells us to preserve them. Although the calculated values mostly match the register defaults even for the 38.4MHz case, there are some differences wrt. what BIOS programs (I noticed at least differences in the MG_PLL_BIAS/IREFTRIM and MG_PLL_BIAS/BIASCAL_EN fields). In the lack of further info on how to program these fields, just do what the spec says and preserve the BIOS state. v2: - Preserve the BIOS programmed reg fields instead of programming them. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by:
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Lucas De Marchi authored
This became dead code with commit 309bd8ed ("drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x"). v2: Move comment about HW behavior to where decision is made to enable MSI (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180523180435.18042-1-lucas.demarchi@intel.com
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Chris Wilson authored
To aide debugging spurious EINVALs, include a debug message every time we emit one from execbuf. References: https://bugs.freedesktop.org/show_bug.cgi?id=106744Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180621080150.8110-1-chris@chris-wilson.co.uk
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Chris Wilson authored
We only need to apply the BIAS for self-relocations into the batchbuffer iff the execobject has any relocations. This suppresses some warnings we may get with a full gtt (so the batch object has wound up at 0 from a previous invocation), but doesn't fix the underlying problem of how we tried to move a pinned batch vma (how we have a pinned user vma outside of execbuf, I do not know, though this being on an aliasing ppgtt means it could be a spurious pinning via the global gtt). One step at a time... References: https://bugs.freedesktop.org/show_bug.cgi?id=106744#c1 Testcase: igt/gem_exec_gttfill # byt (sporadic) Signed-off-by:
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- 20 Jun, 2018 6 commits
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Chris Wilson authored
The guc submission backends expects to only be run from (at least) softirq context, but during our intel_engine_is_idle() check we would call into the tasklet to make sure it was flushed. As this could occur from process context, occasionally we would be caught out using a wait_for_atomic() not from an atomic context: [ 59.939091] WARN_ON_ONCE((1) && !(preempt_count() != 0)) [ 59.939142] WARNING: CPU: 1 PID: 2901 at drivers/gpu/drm/i915/intel_guc_submission.c:615 guc_submission_tasklet+0x784/0xa90 [i915] [ 59.939143] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul snd_hda_intel crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hwdep snd_hda_core e1000e snd_pcm mei_me mei prime_numbers [ 59.939164] CPU: 1 PID: 2901 Comm: gem_exec_schedu Tainted: G U W 4.18.0-rc1-g93475d62c730-drmtip_67+ #1 [ 59.939165] Hardware name: System manufacturer System Product Name/Z170M-PLUS, BIOS 3610 03/29/2018 [ 59.939188] RIP: 0010:guc_submission_tasklet+0x784/0xa90 [i915] [ 59.939189] Code: fc ff ff 80 3d 2f 87 11 00 00 0f 85 80 fb ff ff 48 c7 c6 f8 49 40 c0 48 c7 c7 80 41 3e c0 c6 05 14 87 11 00 01 e8 2c ea d6 d3 <0f> 0b e9 5f fb ff ff 8b 46 38 89 cf 31 c7 83 e7 c0 75 08 39 c1 0f [ 59.939253] RSP: 0018:ffffaafe08a03c10 EFLAGS: 00010286 [ 59.939255] RAX: 0000000000000000 RBX: ffff8f9112c246f0 RCX: 0000000000000001 [ 59.939256] RDX: 0000000080000001 RSI: ffffffff95086d8e RDI: 00000000ffffffff [ 59.939257] RBP: ffff8f9112c24680 R08: 000000009517be77 R09: 0000000000000000 [ 59.939258] R10: 0000000000000000 R11: 0000000000000000 R12: ffff8f9112c24700 [ 59.939259] R13: ffff8f9112c24700 R14: 0000000000000000 R15: ffff8f9112c242a8 [ 59.939260] FS: 00007fc2cc7e5980(0000) GS:ffff8f9136c40000(0000) knlGS:0000000000000000 [ 59.939261] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 59.939262] CR2: 00007fc2cc815040 CR3: 000000021f10e003 CR4: 00000000003606e0 [ 59.939263] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 59.939264] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 59.939265] Call Trace: [ 59.939288] ? intel_engine_is_idle+0x64/0x160 [i915] [ 59.939323] ? intel_engine_dump+0x638/0x890 [i915] [ 59.939327] ? seq_printf+0x49/0x70 [ 59.939353] ? i915_engine_info+0xc8/0x100 [i915] [ 59.939356] ? drm_get_color_range_name+0x20/0x20 [ 59.939361] ? seq_read+0xf1/0x470 [ 59.939365] ? trace_hardirqs_on_caller+0xe0/0x1b0 [ 59.939370] ? full_proxy_read+0x51/0x80 [ 59.939389] ? __vfs_read+0x31/0x170 [ 59.939395] ? do_sys_open+0x13b/0x240 [ 59.939398] ? rcu_read_lock_sched_held+0x6f/0x80 [ 59.939401] ? vfs_read+0x9e/0x140 [ 59.939404] ? ksys_read+0x50/0xc0 [ 59.939409] ? do_syscall_64+0x55/0x190 [ 59.939412] ? entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 59.939420] irq event stamp: 552834 [ 59.939422] hardirqs last enabled at (552833): [<ffffffff940fc74c>] console_unlock+0x3fc/0x600 [ 59.939425] hardirqs last disabled at (552834): [<ffffffff94a0111c>] error_entry+0x7c/0x100 [ 59.939451] softirqs last enabled at (552614): [<ffffffffc02e0f53>] i915_request_add+0x2e3/0x7b0 [i915] [ 59.939470] softirqs last disabled at (552604): [<ffffffffc02e0ecb>] i915_request_add+0x25b/0x7b0 [i915] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106977 Fixes: dd0cf235 ("drm/i915: Speed up idle detection by kicking the tasklets") Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180620135929.23956-1-chris@chris-wilson.co.uk
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Rodrigo Vivi authored
Signed-off-by: -
Radhakrishna Sripada authored
Starting Icelake silicon supports 10-bpc hdmi to support certain media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed in support for 10 bit hdmi. Cc: James Ausmus <james.ausmus@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-18-paulo.r.zanoni@intel.com
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Colin Ian King authored
Currently for the psr_table->tp2_tp3_wakeup_time case 3 there appears to be a copy-paste error from the previous switch statement where dev_priv->vbt.psr.tp1_wakeup_time_us is being assigned and I believe it should be dev_priv->vbt.psr.tp2_tp3_wakeup_time_us that should be assigned instead. Detected by CoverityScan, CID#1470105 ("Copy-paste error") Fixes: 77312ae8 ("drm/i915/psr: vbt change for psr") Signed-off-by:Colin Ian King <colin.king@canonical.com> Reviewed-by:
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Dhinakaran Pandiyan authored
commit 5422b37c ("drm/i915/psr: Kill delays when activating psr back.") removed the call to cancel a scheduled psr_work from psr_disable() and instead added an early return in the work function. But, if the scheduled work item is executed after psr_enable(), we end up printing warnings as PSR is already enabled and active. So, put the cancel_work call back in psr_disable(). Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Fixes: 5422b37c ("drm/i915/psr: Kill delays when activating psr back.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106948Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180618220207.2778-1-dhinakaran.pandiyan@intel.com
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Chris Wilson authored
Along the early error path for igt_switch_to_kernel_context we may try to dereference an invalid error pointer. Instead, return early rather than dump the GEM trace since we haven't yet emitted anything of interest. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Fixes: 09a4c02e ("drm/i915: Look for an active kernel context before switching") Signed-off-by:
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- 19 Jun, 2018 8 commits
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https://github.com/intel/gvt-linuxRodrigo Vivi authored
gvt-next-2018-06-19 - fine-grained per vgpu locking (Colin) - fine-grained vgpu scheduler locking (Colin) - deliver windows guest cursor hotspot info (Tina) - GVT-g BXT support (Colin) - other misc and checker fixes (Chris, Xinyun) Signed-off-by:
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Jani Nikula authored
The hooks aren't supposed to modify the ELD, so use const pointer. As a drive-by fix, use drm_eld_size() to log ELD size. Suggested-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180619124437.10982-1-jani.nikula@intel.com
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Ville Syrjälä authored
The PCH transcoder registers are only 12 bits wide for the hdisplay and hblank_start values. On HSW/BDW the CPU side registers are 13 bits wide. intel_mode_valid() only checks against the higher limit (since we don't know where the mode is to be used), so an extra check is required against the FDI limits. Signed-off-by:
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Ville Syrjälä authored
Validate that all display timings fit within the number of bits we have in the transcoder timing registers. The limits are: hsw+: 4k: vdisplay, vblank_start 8k: everything else gen3+: 4k: h/vdisplay, h/vblank_start 8k: everything else gen2: 2k: h/vdisplay, h/vblank_start 4k: everything else Also document the fact that the mode_config.max_width/height limits refer to just the max framebuffer dimensions we support. Which may be larger than the max hdisplay/vdisplay. Signed-off-by:
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Ville Syrjälä authored
No point in having this extra indireciton for the cursor max size. So drop the defines and just write out the raw numbers. Makes it easier to see what's going on. Signed-off-by:
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Ville Syrjälä authored
Use the '[PROP:id:name]' format I introduced for the core in the driver debug messages as well. Signed-off-by:
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Vathsala Nagaraju authored
Adds new psrwake options defined in the below table. Platform PSR wake options vbt version KBL/CFL/WHL All(205+) BXT Uses old interpretation. CNL/ICL+ All(205+) GLK All(205+) SKL All PV releases (Check for 205+ might help but cannot be foolproof) We will continue with newer interpretation for SKL from 205. v2: Jani Keep the bdb version check. v3: Apply newer version for skl from 205+(DK). Add (version check && platform list) (Jani). Add bdb version for each platform in commit message(DK). Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Puthikorn Voravootivat <puthik@chromium.org> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ashutosh D Shukla <ashutosh.d.shukla@intel.com> Cc: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by:Vathsala Nagaraju <vathsala.nagaraju@intel.com> Reviewed-by:
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Arnd Bergmann authored
This function has been unused since commit 5ed0bdf2 ("drm: i915: Use nsec based interfaces"). Let's remove the definition as well now to help get rid of all uses of 'timespec'. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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- 18 Jun, 2018 11 commits
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Dhinakaran Pandiyan authored
This patch enables hotplug interrupts for DP over TBT output on TC ports. The TBT interrupts are enabled and handled irrespective of the actual output type which could be DP Alternate, DP over TBT, native DP or native HDMI. Cc: Animesh Manna <animesh.manna@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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Dhinakaran Pandiyan authored
The hotplug interrupts for the ports can be routed to either North Display or South Display depending on the output mode. DP Alternate or DP over TBT outputs will have hotplug interrupts routed to the North Display while interrupts for legacy modes will be routed to the South Display in PCH. This patch adds hotplug interrupt handling support for DP Alternate mode. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
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Dhinakaran Pandiyan authored
The Graphics System Event(GSE) interrupt bit has a new location in the GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only DE_MISC interrupt that was enabled, with this change we don't enable/handle any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out the register change. v2: from DK raw_reg_[read/write], branch prediction hint and drop platform check (Mika) v3: From DK Early re-enable of master interrupt (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: -
Paulo Zanoni authored
While I don't see any issue with the way these macros are being called today, let's protect them against operator precedence issues before they happen. Reviewed-by:
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Paulo Zanoni authored
Since I'm touching the file I might as well fix this class of errors since they are just a few. Also drive-by fix the styling of the VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before the tabs. Reviewed-by:
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Paulo Zanoni authored
Because OCD. Now seriously, commit 1aa920ea ("drm/i915: add register macro definition style guide") has finally established a coding standard to be followed by the rest of the file, and I've been trying to request everybody to adhere to that since then. The problem is that when someone adds a new line to a register that has the wrong style, these people generally propagate the wrong style and I have to keep asking them to drive-by fix the whole register, which is not something I like to do and also creates extra work for them. Or I can ignore the propagation of the wrong coding style and feel anxious about it. On top of that, we now have our CI happily reminding us about these problems, which makes everything worse. So IMHO the best way to proceed is to fix the spacing issues in the file once and for all. Contributors will stop propagating the bad style when adding new bits to registers that already have bad style, we will stop asking them to redo their patches and the CI emails will become more relevant by having less semi-false errors. Yes, there will be some pain involved for backporters, but at least spacing issues like that are easy to spot and fix in the patch files. This patch was generated by: ../../../../scripts/checkpatch.pl -f --strict --types SPACING \ --fix-inplace i915_reg.h I manually checked the output and everything seems sane. v2: Single conflict around the addition of DP_TP_CTL_LINK_TRAIN_PAT4. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by:
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Radhakrishna Sripada authored
Expand the Maud/Naud table according to DP 1.4 spec to include entries for 810 MHz clock. This is required for audio to work with HBR3. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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José Roberto de Souza authored
Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. Reviewed-by:
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José Roberto de Souza authored
Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. v2: Fixing GT level of some ids Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Chris Wilson authored
Having the w/a registers as an open-coded table leaves a trap for the unwary; it would be easy to miss incrementing the LRI counter when adding a new register to the list. Instead, pull the list of registers into a table, so that we only need add new registers to that table rather than try and remember important side-effects of earlier chunks of GPU instructions. Suggested-by:
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Chris Wilson authored
Since we trigger 10,000s of hangs and resets during selftesting, we emit many, many thousands of lines of useless debug messages. Reduce the frequency by only logging a change in state of a guilty context. Fixes: 14921f3c ("drm/i915: Fix context ban and hang accounting for client") Signed-off-by:
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