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  1. 24 Jun, 2021 5 commits
  3. 18 Jun, 2021 4 commits
    • Suman Anna's avatar
      arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs · d71abfcc
      Suman Anna authored 
      Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within the MAIN domain on the TI AM642 EVM
and SK boards. These nodes are assigned to the respective rproc device
nodes as well. The first region will be used as the DMA pool for the rproc
devices, and the second region will furnish the static carveout regions
for the firmware memory.

An additional reserved memory node is also added to reserve a portion of
the DDR memory to be used for performing inter-processor communication
between all the remote processors running RTOS or baremetal firmwares.
8 MB of memory is reserved for this purpose, and this accounts for all
the vrings and vring buffers between all the possible pairs of remote
processors.

The current carveout addresses and sizes are defined statically for each
rproc device. The R5F processors do not have an MMU, and as such require
the exact memory used by the firmwares to be set-aside. The firmware
images do not require any RSC_CARVEOUT entries in their resource tables
to allocate the memory for firmware memory segments.

NOTE:
1. The R5F1 carveouts are needed only if the R5F cluster is running in
   Split (non Single-CPU) mode. The reserved memory nodes can be disabled
   later on if there is no use-case defined to use the corresponding
   remote processor.
2. The AM64x SoCs do not have any DSPs and one less R5F cluster compared
   to J721E SoCs. So, while the carveout memories reserved for the R5F
   clusters present on the SoC match to those on J721E, the overall
   memory map reserved for firmwares is quite different. The number of
   R5F clusters on AM64x SoCs are same as on J7200 SoCs, but the AM64x
   SoCs also have an additional M4F core, so the RTOS IPC memory region
   is 1 MB higher than on J7200 SoCs.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Reviewed-by: default avatarPraneeth Bajjuri <praneeth@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-4-s-anna@ti.com
      d71abfcc
    • Suman Anna's avatar
      arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs · 0afadba4
      Suman Anna authored 
      Add the required 'mboxes' property to all the R5F processors for the
TI AM642 EVM and SK boards. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Reviewed-by: default avatarPraneeth Bajjuri <praneeth@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-3-s-anna@ti.com
      0afadba4
    • Suman Anna's avatar
      arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes · a4f221cd
      Suman Anna authored 
      The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. Both the R5F clusters are present within the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a new "Single-CPU" mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
The mode is restricted to "Single-CPU" on some devices with the
appropriate eFuse bit set, but the most common devices support both
modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM)
internal memories for each core split between two banks - ATCM and
BTCM (further interleaved into two banks). The TCMs of both Cores
are combined in Single-CPU mode to provide a larger 128 KB of memory.
The other notable difference is that the TCMs are spaced 1 MB apart
on these SoCs unlike the existing SoCs.

Add the DT nodes for both these MAIN domain R5F cluster/subsystems,
the two R5F cores are added as child nodes to each of the corresponding
R5F cluster node. Both the clusters are configured to run in Split mode
by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
  MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode)
  MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode)

NOTE:
A R5FSS cluster can be configured in "Single-CPU" mode by using a
value of 2 for the "ti,cluster-mode" property. Value of 1 is not
permitted (fails the dtbs_check).
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Reviewed-by: default avatarPraneeth Bajjuri <praneeth@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210615195718.15898-2-s-anna@ti.com
      a4f221cd
    • Nishanth Menon's avatar
      Merge tag '20210327143117.1840-2-s-anna@ti.com' of... · b75596db
      Nishanth Menon authored 
      Merge tag '20210327143117.1840-2-s-anna@ti.com' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc into ti-k3-dts-next

v5.13-rc1 + 20210327143117.1840-2-s-anna@ti.com

* tag '20210327143117.1840-2-s-anna@ti.com' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc:
  dt-bindings: remoteproc: k3-r5f: Update bindings for AM64x SoCs
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      b75596db
  5. 17 Jun, 2021 11 commits
  7. 15 Jun, 2021 13 commits
  9. 14 Jun, 2021 7 commits
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