- 20 Sep, 2022 4 commits
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Christian König authored
Allows submitting jobs as gang which needs to run on multiple engines at the same time. All members of the gang get the same implicit, explicit and VM dependencies. So no gang member will start running until everything else is ready. The last job is considered the gang leader (usually a submission to the GFX ring) and used for signaling output dependencies. Each job is remembered individually as user of a buffer object, so there is no joining of work at the end. v2: rebase and fix review comments from Andrey and Yogesh v3: use READ instead of BOOKKEEP for now because of VM unmaps, set gang leader only when necessary v4: fix order of pushing jobs and adding fences found by Trigger. v5: fix job index calculation and adding IBs to jobs v6: fix typo found by Alex Signed-off-by:Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Christian König authored
Allows submitting jobs as gang which needs to run on multiple engines at the same time. Basic idea is that we have a global gang submit fence representing when the gang leader is finally pushed to run on the hardware last. Jobs submitted as gang are never re-submitted in case of a GPU reset since this won't work and will just deadlock the hardware immediately again. v2: fix logic inversion, improve documentation, fix rcu Signed-off-by:
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Christian König authored
Similar to what we did for VCN3 use the job instead of the parser entity. Cleanup the coding style quite a bit as well. v2: merge improved application check into this patch v3: finally fix the check v4: limit to the correct engine Signed-off-by:
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Yury Zhuravlev authored
Instead of using RPM speed, we will use a function from vega20 based on PWM registers. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Yury Zhuravlev <stalkerg@gmail.com> Signed-off-by:
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- 19 Sep, 2022 36 commits
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Christian König authored
This reverts commit 250195ff. The job should now be initialized when we reach the parser functions. v2: merge improved application check into this patch v3: back to the original test, but use the right ring Signed-off-by:
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Christian König authored
Initialize the entity for the CS and scheduler job much earlier. v2: fix job initialisation order and use correct scheduler instance Signed-off-by:
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Christian König authored
Return early on success and so remove all those "if (r)" in the error path. Signed-off-by:
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Christian König authored
Cleanup the coding style and function names to represent the data they process for pass2 as well. Go over the chunks only twice now instead of multiple times. v2: fix job initialisation order and use correct scheduler instance v3: try to move all functional changes into a separate patch. v4: separate reordering, pass1 and pass2 change v5: fix va_start calculation v6: fix user fence check Signed-off-by:
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YiPeng Chai authored
V3: [Why]: Since ASICs using smu v13_0_2 have called smu .suspend before calling amdgpu_pm_sysfs_fini, pm.dpm_enabled was already set to 0 when smu .suspend was called. This makes it impossible to delete all pm sys nodes. [How]: Since all functions in amdgpu_pm_sysfs_fini have their own condition checks, so the first conditional check in amdgpu_pm_sysfs_fini can be removed. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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YiPeng Chai authored
V3: Fixed psp fence and memory issues for the asic using smu v13_0_2 when removing amdgpu device. [Why]: 1. psp_suspend->psp_free_shared_bufs-> psp_ta_free_shared_buf-> amdgpu_bo_free_kernel-> ...->amdgpu_bo_release_notify-> amdgpu_fill_buffer psp will free vram memory used by psp when psp_suspend is called. But for the asic using smu v13_0_2, because psp_suspend is called before adev->shutdown is set to true when removing the first hive device, amdgpu fill_buffer will be called, which will cause fence issues when evicting all vram resources in amdgpu vram mgr_fini. 2. Since psp_hw_fini is not called after calling psp_suspend and psp_suspend only calls psp_ring_stop, the psp ring memory will not be released when amdgpu device is removed. [How]: 1. Set shutdown to true before calling amdgpu_device_gpu_recover, then amdgpu_fill_buffer will not be called when psp_suspend is called. 2. Free psp ring memory in psp_sw_fini. Signed-off-by: -
YiPeng Chai authored
Adjust removal control flow for smu v13_0_2: During amdgpu uninstallation, when removing the first device, the kernel needs to first send a mode1reset message to all gpu devices. Otherwise, smu initialization will fail the next time amdgpu is installed. V2: 1. Update commit comments. 2. Remove the global variable amdgpu_device_remove_cnt and add a variable to the structure amdgpu_hive_info. 3. Use hive to detect the first removed device instead of a global variable. V3: 1. Update commit comments. 2. Split a patch into multiple patches. 3. The current patch does: a. Add a work mode of AMDGPU_RESET_FOR_DEVICE_REMOVE into the existing gpu recover path, which make all devices in hive list only have HW reset but no resume (except the base IP). b. Call AMDGPU_RESET_FOR_DEVICE_REMOVE and AMDGPU_NEED_FULL_RESET mode of amdgpu_device_gpu_recover in amdgpu_pci_remove when removing the first device in hive list. c. When removing the first device, the IP blocks keyword function call sequence is as follows: .suspend->mode1reset->.resume(basic ip)->.hw_fini->.early_fini->.sw_fini. ^ | |-<----------<---------<----| The first three sequences are because of a call to amdgpu_device_gpu_recover. The three sequences will be executed in a loop until all devices in the hive list are iterated. The sequences starting from .hw_fini only apply to the first device. Since .suspend has been called before, except the resumed phase1 basic ip blocks, all other ip blocks .hw_fini of current device will do nothing. d. When removing other devices, the calling sequences is the same as legacy: .hw_fini -> .early_fini -> .sw_fini. Since .suspend has been called when removing the first device, except the resumed phase1 basic ip blocks, all of other ip blocks .hw_fini of current device will do nothing. Signed-off-by: -
Aric Cyr authored
This version brings along following fixes: - Fix urgent latency override for DCN32/DCN321 - Correct hostvm flag in DCN31 - Added new Asic Id for DCN301 - Adjust to 2 phys in DCN301 - Update dummy P-state search to use DCN32 DML - Increase dcn315 pstate change latency - Disable OTG WA for the plane_state NULL case on DCN314 - Update dccg based on HW delta - Correct num_dsc for DCN314 - Fix DP DSC compliance failure with DCN314 - Refactor edp power sequencer codes - update gamut remap if plane has changed - Skip audio setup when audio stream is enabled - Display distortion after hotplug LG Ultrafine 5K tiled display - Fix DP MST timeslot issue when fallback happened - Uncomment SubVP pipe split assignment in driver - Enable committing subvp config - Do second pass through DML for DET calculation - Don't allocate DET for phantom pipes - Modify DML to adjust Vstartup Position - Ignore k1/k2 values for virtual signal to avoid assert - Fix failures of disabling primary planes - Do not compare integers of different widths - Fix empty slot problem of EDID management - Revise Sink device string ID width in dmub psr - Log vertical interrupt 1 for debug Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Charlene Liu authored
[why] num_dsc is 3 for dcn314 based on HW capablity. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Wenjing Liu authored
[Why] There is a coding error when moving dp disable link phy to hw sequencer, where the receiver power control is missed during this refactor. [how] 1. Add back missing receiver power control in disable link phy. 2. minor modifications to ensure there is no undesired sequence changes in dp link enable/disable. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Charlene Liu authored
[why] update hw dccg based on HW delta, and reuse common src code Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Alvin Lee authored
[Why & How] If we find that DML requires pipe split, run through DML again because the DET allocation per pipe must be re-assigned. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Extend existing OTG state collection function to include the vertical interrupt 1 state. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Robin Chen authored
[Why] The Sink device string ID1/ID2 use 5 bytes instead of 6 bytes, so the driver should compare the first 5 bytes only. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Robin Chen <po-tchen@amd.com> Tested-by:
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muansari authored
[WHY] The Vstartup position should be as late as possible to maximize power saving with the current. Calculation of Vstartup in DML does not take into account as SDP signal. [HOW] Made necessary changes to calculate the correct Vstartup position in DML to account for AS SDP * Overriding the VBlankNom value in certain cases otherwise it will use the default value * Bypassing the condition for adjust_sync_Vstartup * Overriding vblank_nom_input with VBlankNom that is set in the SW Layer Reviewed-by:
muansari <muansari@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] This shouldn't trigger during tiled display hotplug/unplug but it does because one of the tiles can end up with a NULL plane state. This also doesn't guard against the hang that it was originally trying to resolve, and can instead cause DIO corruption due to OTG sync being lost. [How] This was reverted at one point out of DCN31 so revert it here too. Reviewed-by:
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Daniel Miess authored
[Why] DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE shift and mask being missing [How] Add in shift and mask for ICH_RESET_AT_END_OF_LINE Reviewed-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why and How] Enable committing subvp config through DMCUB for DCN32 Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Jaehyun Chung authored
[Why] v1_5 display object table has no way for connectors to indicate which slot they are a part of, resulting in additional empty slots to appear in EDID management UI. [How] Assume that all connectors belong to the same slot. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jaehyun Chung <jaehyun.chung@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by:
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Dmytro Laktyushkin authored
[Why & How] Update after new measurment came in Reviewed-by:
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Rodrigo Siqueira authored
[Why and How] We are hitting k1/k2 assert when we are using a virtual signal in the test; as a result, we are failing some automated tests with a false positive. This commit addresses this issue by ignoring the assert condition if we use SIGNAL_TYPE_VIRTUAL. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Alvin Lee authored
[Why & How] We should not allocate any DET for the phantom pipes. Reviewed-by:
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Cruise Hung authored
[Why] When USB4 DP link training failed and fell back to lower link rate, the time slot calculation uses the verified_link_cap. And the verified_link_cap was not updated to the new one. It caused the wrong VC payload time-slot was allocated. [How] Updated verified_link_cap with the new one from cur_link_settings after the LT completes successfully. Reviewed-by:
Cruise Hung <Cruise.Hung@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During hot plug of specific 5K tiled display, sometimes both the tiles are not synchronized resulting in distortion. The reason is that otgs of both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa) is applied for bandwidth optimization. The otg workaround reenables otg but otg synchronization context is not reset and hence dc_trigger_sync() does not resynchronize otg again. [How] Implement reset_sync_context_for_pipe() to reset the otg synchronization context for the disabled pipe and its slave pipes when otg workaround is applied. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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George Shen authored
[Why] Current DCN3.2 logic for finding the dummy P-state index uses the DCN3.0 DML validation function instead of DCN3.2 DML. This can result in either unexpected DML VBA values, or unexpected dummy P-state index to be used. [How] Update the dummy P-state logic to use DCN3.2 DML validation function. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Charlene Liu authored
[why] Expose few dchubbun functions in dcn31 and dcn32 to leverage. Reviewed-by:
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Pavle Kotarac authored
[WHY] New dcn301 has 2 less phys Reviewed-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Tested-by:
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Pavle Kotarac authored
[WHY] Adding new asic id for dcn301 Reviewed-by:
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Sherry Wang authored
[Why] Hostvm should be enabled/disabled accordding to the status of riommu_active, but hostvm always be disabled on DCN31 which causes underflow [How] Set correct hostvm flag on DCN31 Reviewed-by:
Sherry Wang <Yao.Wang1@amd.com> Tested-by:
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George Shen authored
[Why] The urgent latency override is useful when debugging issues relating to underflow. Current overridden variable is not correct and has no effect on DCN3.2 and DCN3.21 DML calculations. [How] For DCN3.2 and DCN3.21, override the correct urgent latency variable when bounding box override is present. Reviewed-by:
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Alvin Lee authored
[Why & How] Uncomment SubVP pipe split assignment in driver since FW headers are now promoted Reviewed-by:
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zhikzhai authored
[why] We have minimal pipe split transition method to avoid pipe allocation outage.However, this method will invoke audio setup which cause audio output stuck once pipe reallocate. [how] skip audio setup for pipelines which audio stream has been enabled Reviewed-by:
zhikzhai <zhikai.zhai@amd.com> Tested-by:
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Hugo Hu authored
[Why] The desktop plane and full-screen game plane may have different gamut remap coefficients, if switching between desktop and full-screen game without updating the gamut remap will cause incorrect color. [How] Update gamut remap if planes change. Reviewed-by:
Hugo Hu <hugo.hu@amd.com> Tested-by:
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Ian Chen authored
[Why & How] Move extra panel power sequencer settings into panel_cofig struct. Reviewed-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: - Port DCN30 420 logic to DCN32 - Remove some unused definitions from DCN32/321 - Remove dp dig pixle rate div policy from dcn314 - Fix dcn315 reading of memory channel count and width - Fix SubVP and ODM relevant issues - Fix pipe split, MPO and ODM relevant issues - Support proper mst payload removal when link is not in mst mode in dc - Assume an LTTPR is always present on fixed_vs links - Rework recent update PHY state commit - Add debug option and logs Acked-by:
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