- 20 Dec, 2022 8 commits
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Alex Deucher authored
It's handled by GFXOFF for SDMA 5.x and SMU saves the state on SDMA 4.x. Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
gfxhub registers are part of gfx IP and should not need to be changed. Doing so without disabling gfxoff can hang the gfx IP. v2: add comments explaining why we can skip the interrupt control for S0i3 Reviewed-by: -
Alex Deucher authored
gfxhub registers are part of gfx IP and should not need to be changed. Doing so without disabling gfxoff can hang the gfx IP. v2: add comments explaining why we can skip the interrupt control for S0i3 Reviewed-by: -
Alex Deucher authored
gfxhub registers are part of gfx IP and should not need to be changed. Doing so without disabling gfxoff can hang the gfx IP. v2: add comments explaining why we can skip the interrupt control for S0i3 Reviewed-by: -
Arnd Bergmann authored
The activity_monitor_external[] array is too big to fit on the kernel stack, resulting in this warning with clang: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.c:1438:12: error: stack frame size (1040) exceeds limit (1024) in 'smu_v13_0_7_get_power_profile_mode' [-Werror,-Wframe-larger-than] Use dynamic allocation instead. It should also be possible to have single element here instead of the array, but this seems easier. v2: fix up argument to sizeof() (Alex) Fixes: 334682ae ("drm/amd/pm: enable workload type change on smu_v13_0_7") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Arnd Bergmann authored
The .set_odm_combine callback pointer was added twice, causing a harmless -Wextra warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:258:36: error: initialized field overwritten [-Werror=override-init] 258 | .set_odm_combine = optc314_set_odm_combine, | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:258:36: note: (near initialization for 'dcn314_tg_funcs.set_odm_combine') Fixes: 5ade1b95 ("drm/amd/display: Add OTG/ODM functions") Signed-off-by: -
Philip Yang authored
If kfd_process_device_init_vm returns failure after vm is converted to compute vm and vm->pasid set to compute pasid, KFD will not take pdd->drm_file reference. As a result, drm close file handler maybe called to release the compute pasid before KFD process destroy worker to release the same pasid and set vm->pasid to zero, this generates below WARNING backtrace and NULL pointer access. Add helper amdgpu_amdkfd_gpuvm_set_vm_pasid and call it at the last step of kfd_process_device_init_vm, to ensure vm pasid is the original pasid if acquiring vm failed or is the compute pasid with pdd->drm_file reference taken to avoid double release same pasid. amdgpu: Failed to create process VM object ida_free called for id=32770 which is not allocated. WARNING: CPU: 57 PID: 72542 at ../lib/idr.c:522 ida_free+0x96/0x140 RIP: 0010:ida_free+0x96/0x140 Call Trace: amdgpu_pasid_free_delayed+0xe1/0x2a0 [amdgpu] amdgpu_driver_postclose_kms+0x2d8/0x340 [amdgpu] drm_file_free.part.13+0x216/0x270 [drm] drm_close_helper.isra.14+0x60/0x70 [drm] drm_release+0x6e/0xf0 [drm] __fput+0xcc/0x280 ____fput+0xe/0x20 task_work_run+0x96/0xc0 do_exit+0x3d0/0xc10 BUG: kernel NULL pointer dereference, address: 0000000000000000 RIP: 0010:ida_free+0x76/0x140 Call Trace: amdgpu_pasid_free_delayed+0xe1/0x2a0 [amdgpu] amdgpu_driver_postclose_kms+0x2d8/0x340 [amdgpu] drm_file_free.part.13+0x216/0x270 [drm] drm_close_helper.isra.14+0x60/0x70 [drm] drm_release+0x6e/0xf0 [drm] __fput+0xcc/0x280 ____fput+0xe/0x20 task_work_run+0x96/0xc0 do_exit+0x3d0/0xc10 Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
Should only destroy the ib_mem and let process cleanup worker to free the outstanding BOs. Reset the pointer in pdd->qpd structure, to avoid NULL pointer access in process destroy worker. BUG: kernel NULL pointer dereference, address: 0000000000000010 Call Trace: amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel+0x46/0xb0 [amdgpu] kfd_process_device_destroy_cwsr_dgpu+0x40/0x70 [amdgpu] kfd_process_destroy_pdds+0x71/0x190 [amdgpu] kfd_process_wq_release+0x2a2/0x3b0 [amdgpu] process_one_work+0x2a1/0x600 worker_thread+0x39/0x3d0 Signed-off-by:
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- 15 Dec, 2022 32 commits
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Candice Li authored
Add poison mode query support on df v4_3. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Candice Li authored
Add df v4_3 header files. Signed-off-by:
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Evan Quan authored
Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock. And update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock. User applications can better utilize these IOCTLs to get needed informations. Increase the minor version number to indicate that the new flags are available. Proposed mesa patch: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/278Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Otherwise, some UMD tools will treate them as 0 at default while actually they are not. Signed-off-by:
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Evan Quan authored
Expose those informations to UMD who need them as for standard profiling mode. Signed-off-by:
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Evan Quan authored
Enable peak profiling mode shader/memory clock reporting for powerplay framework. Signed-off-by:
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Evan Quan authored
Enable peak profiling mode shader/memory clocks reporting for swsmu framework. Signed-off-by:
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Evan Quan authored
The API is not in use. And it's unlikely to be used in the future either. Signed-off-by:
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Sung Joon Kim authored
The missing DPCD definitions from DP2.0 spec is as follows: DOWNSPREAD_CTRL (107h): FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (bit 6) For sink devices that support Adaptive-Sync operation and Panel Replay DPRX_FEATURE_ENUMERATION_LIST_CONT_1 (2214h): ADAPTIVE_SYNC_SDP_SUPPORTED (bit 0) Bit to check sink device has Adaptive-Sync capability AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (bit 1) A sink device that clears this bit will generate VSync pulse leading edge of the HDMI output on the line count at which Adaptive-Sync SDP is received as long as source device transmits Adaptive-Sync SDP either in first line or first 3840 pixel cycles of the line whichever occurs first. VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (bit 4) Bit to check sink device has SDP framework version 1 capability Signed-off-by:
Sung Joon Kim <Sungjoon.Kim@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Paulo Miguel Almeida authored
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs _ATOM_DISPLAY_OBJECT_PATH, _ATOM_DISPLAY_OBJECT_PATH_TABLE, _ATOM_OBJECT_TABLE, GOP_VBIOS_CONTENT _ATOM_GPIO_VOLTAGE_OBJECT_V3 and refactor the rest of the code accordingly. It's worth mentioning that doing a build before/after this patch results in no binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/239 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by:
Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com> Signed-off-by:
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Tao Zhou authored
1. no need to query poison mode on SRIOV guest side, host can handle it. 2. define the function to simplify code. v2: rename amdgpu_ras_poison_mode_query to amdgpu_ras_query_poison_mode. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Tao Zhou authored
Support VCN/JPEG RAS in both bare metal and SRIOV environment. v2: update commit description. Signed-off-by:
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Tao Zhou authored
Injection on guest is not allowed. v2: return directly in SRIOV environment. Signed-off-by:
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Tao Zhou authored
Inform host and let host handle consumption interrupt. Signed-off-by:
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Tao Zhou authored
Send message to PF if VF receives RAS poison consumption interrupt. Signed-off-by:
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Tao Zhou authored
Send handling request to host. Signed-off-by:
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Tao Zhou authored
Send message to host and host will handle it. v2: split the patch into two parts, one is for mxgpu ai and another one is for common poison consumption handler. Signed-off-by:
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Alvin Lee authored
[Description] - Current policy does not support HDMI VRR by default, so we cannot enable FPO / SubVP (DRR) cases Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: -Fix array index out of bound error -Speed up DML fast vadlaite -Implement multiple secure display -MST HDCP for multiple display -Add DPIA notification -Add support for three new square pattern variant Reviewed-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Fangzhi Zuo authored
[Why && How] On dcn32, HW supports odm transition in fast update. Hence this error message is considered false positive. Downgrade the error level to avoid catching unnecessary attention. Reviewed-by:
Dillon Varone <Dillon.Varone@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] DP2.1 specs has brought 3 new variants of sqaure patterns with different pre-shoot and de-emphasis equalization requirements. The commit adds logic to identify these variants and apply corresponding eqaulization requirements into hardware lane settings. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY] Subvp portion validation currently assumes that if vlevel provided does not support pstate, then none will, and so subvp is not used. [HOW] After get vlevel, use lowest vlevel that supports pstate if it exists, and use that for subvp validation. Reviewed-by:
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Samson Tam authored
[Why] When we have a PSR display, we will not be requesting data from memory anymore. So we report back true for no memory request case. [How] Check for PSR by checking PSR version in link settings Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - When merging a pipe that was previously pipe split, we need to also clear the link resources or the next stream/plane that uses the pipe may have an incorrect link resource state Reviewed-by:
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Mustapha Ghaddar authored
[WHY] Adding the new DPIA NOTIFY packets from DMUB As per the design with Cruise to account for 250ms response delay otherwise [HOW] Added th DPIA NOTIFY logic as per DMUB logic Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Roman Li authored
[Why] In case of failure to resume MST topology after suspend, an emtpty mst tree prevents further mst hub detection on the same connector. That causes the issue with MST hub hotplug after it's been unplug in suspend. [How] Stop topology manager on the connector after detecting DM_MST failure. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] in dc_link_dp there still exist a few places where we call dio encoders without checking current enabled encoder type. The change is to make these places to call hwss equivalent functions so it won't mistakenly program a wrong type encoder. Reviewed-by:
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Leo (Hanghong) Ma authored
Workaround no longer needed. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Roman Li authored
[Why] Fixing smatch error: dm_resume() error: we previously assumed 'aconnector->dc_link' could be null [How] Check if dc_link null at the beginning of the loop, so further checks can be dropped. Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Ian Chen authored
[WHY] It causes regression AMD source will not write DPCD 340. Reviewed-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - FW scheduling algorithm doesn't take into account of it's a center timing - This affects where the subvp mclk switch can be scheduled (prevents HUBP vline interrupt from coming in if scheduled incorrectly) - Block subvp center timing cases for now Reviewed-by:
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Dillon Varone authored
[Description] Modify soc BB to reduce expected sdp bandwidth and align with measurements to fix underflow issues. Reviewed-by:
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