- 01 Dec, 2022 18 commits
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Abel Vesa authored
Add device tree bindings for global clock controller on SM8550 SoCs. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-2-abel.vesa@linaro.org
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Lin, Meng-Bo authored
Similar to msm8916, msm8939 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reference: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ruSigned-off-by:Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by:
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Minghao Chi authored
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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Robert Marko authored
It appears that having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for all parent clocks in parent_data. Fixes: ae55ad32 ("clk: qcom: ipq8074: convert to parent data") Co-developed-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Christian Marangi authored
Modernize the krait-cc driver to parent-data API and refactor to drop any use of parent_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. .name is also declared to save compatibility with old DT. While at it also drop some hardcoded index and introduce an enum to make index values more clear. Signed-off-by:
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Christian Marangi authored
clk_register is now deprecated. Convert the driver to devm_clk_hw_register. Signed-off-by:
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Christian Marangi authored
Some bootloader may leave the system in an even more undefined state with the secondary mux of L2 or other cores sourcing out of the acpu_aux parent. This results in the clk set to the PXO rate or a PLL8 rate. The current logic to reset the mux and set them to a defined state only handle if the mux are configured to source out of QSB. Change this and force a new and defined state if the current clk is lower than the aux rate. This way we can handle any wrong configuration where the mux is sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1), PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz). Signed-off-by:
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Christian Marangi authored
clk-krait ignore any rate change if clk is not flagged as enabled. Correctly enable the secondary mux and div clk to correctly change rate instead of silently ignoring the request. Signed-off-by:
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Christian Marangi authored
The secondary mux parent order is swapped. This currently doesn't cause problems as the secondary mux is used for idle clk and as a safe clk source while reprogramming the hfpll. Each mux have 2 or more output but he always have a safe source to switch while reprogramming the connected pll. We use a clk notifier to switch to the correct parent before clk core can apply the correct rate. The parent to switch is hardcoded in the mux struct. For the secondary mux the safe source to use is the qsb parent as it's the only fixed clk as the acpus_aux is a pll that can source from pxo or from pll8. The hardcoded safe parent for the secondary mux is set to index 0 that in the secondary mux map is set to 2. But the index 0 is actually acpu_aux in the parent list. Fix the swapped parents to correctly handle idle frequency and output a sane clk_summary report. Signed-off-by:
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Christian Marangi authored
Use devm variant for clk notifier register and correctly handle free resource on driver remove. Signed-off-by:
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Christian Marangi authored
Currently div2 value is applied to the wrong bits. This is caused by a bug in the code where the shift is done only for lpl, for anything else the mask is not shifted to the correct bits. Fix this by correctly shift if lpl is not supported. Fixes: 4d7dc77b ("clk: qcom: Add support for Krait clocks") Signed-off-by:
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Christian Marangi authored
krait-cc use this driver for the secondary mux. Register it as a clk provider to correctly use this clk in other drivers. Signed-off-by:
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Robert Marko authored
Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers. So, port the downstream resets and avoid using magic values for mask, construct mask for resets which require multiple bits to be set/cleared. Signed-off-by:
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Robert Marko authored
Add bindings for the missing networking resets found in IPQ8074 GCC. Signed-off-by:
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Robert Marko authored
This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations. Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro. However, this is not sufficient anymore for newer SoC-s like IPQ8074, IPQ6018 and more, since their networking resets require multiple bits to be asserted in order to properly reset the HW block completely. So, in order to allow asserting multiple bits add "bitmask" field to qcom_reset_map, and then use that bitmask value if its populated in the driver, if its not populated, then we just default to existing behaviour and calculate the bitmask on the fly. Signed-off-by:
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Douglas Anderson authored
The two devices managed by lpasscorecc-sc7180.c each had their own "struct dev_pm_ops". This is not needed. They are exactly the same and the structure is "static const" so it can't possible change. combine the two. This matches what's done for sc7280. This should be a noop other than saving a few bytes. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Douglas Anderson authored
The sc7180 lpass clock controller's pm_runtime usage wasn't broken quite as spectacularly as the sc7280's pm_runtime usage, but it was still broken. Putting some printouts in at boot showed me this (with serial console enabled, which makes the prints slow and thus changes timing): [ 3.109951] DOUG: my_pm_clk_resume, usage=1 [ 3.114767] DOUG: my_pm_clk_resume, usage=1 [ 3.664443] DOUG: my_pm_clk_suspend, usage=0 [ 3.897566] DOUG: my_pm_clk_suspend, usage=0 [ 3.910137] DOUG: my_pm_clk_resume, usage=1 [ 3.923217] DOUG: my_pm_clk_resume, usage=0 [ 4.440116] DOUG: my_pm_clk_suspend, usage=-1 [ 4.444982] DOUG: my_pm_clk_suspend, usage=0 [ 14.170501] DOUG: my_pm_clk_resume, usage=1 [ 14.176245] DOUG: my_pm_clk_resume, usage=0 ...or this w/out serial console: [ 0.556139] DOUG: my_pm_clk_resume, usage=1 [ 0.556279] DOUG: my_pm_clk_resume, usage=1 [ 1.058422] DOUG: my_pm_clk_suspend, usage=-1 [ 1.058464] DOUG: my_pm_clk_suspend, usage=0 [ 1.186250] DOUG: my_pm_clk_resume, usage=1 [ 1.186292] DOUG: my_pm_clk_resume, usage=0 [ 1.731536] DOUG: my_pm_clk_suspend, usage=-1 [ 1.731557] DOUG: my_pm_clk_suspend, usage=0 [ 10.288910] DOUG: my_pm_clk_resume, usage=1 [ 10.289496] DOUG: my_pm_clk_resume, usage=0 It seems to be doing roughly the right sequence of calls, but just like with sc7280 this is more by luck than anything. Having a usage of -1 is just not OK. Let's fix this like we did with sc7280. Signed-off-by:
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Douglas Anderson authored
The pm_runtime usage in lpass-sc7280 was broken in quite a few ways. Specifically: 1. At the end of probe it called "put" twice. This is a no-no and will end us up with a negative usage count. Even worse than calling "put" twice, it never called "get" once. Thus after bootup it could be seen that the runtime usage of the devices managed by this driver was -2. 2. In some error cases it manually called pm_runtime_disable() even though it had previously used devm_add_action_or_reset() to set this up to be called automatically. This meant that in these error cases we'd double-call pm_runtime_disable(). 3. It forgot to call undo pm_runtime_use_autosuspend(), which can sometimes have subtle problems (and the docs specifically mention that you need to undo this function). Overall the above seriously calls into question how this driver is working. It seems like a combination of "it doesn't", "by luck", and "because of the weirdness of runtime_pm". Specifically I put a printout to the serial console every time the runtime suspend/resume was called for the two devices created by this driver (I wrapped the pm_clk calls). When I had serial console enabled, I found that the calls got resumed at bootup (when the clk core probed and before our double-put) and then never touched again. That's no good. [ 0.829997] DOUG: my_pm_clk_resume, usage=1 [ 0.835487] DOUG: my_pm_clk_resume, usage=1 When I disabled serial console (speeding up boot), I got a different pattern, which I guess (?) is better: [ 0.089767] DOUG: my_pm_clk_resume, usage=1 [ 0.090507] DOUG: my_pm_clk_resume, usage=1 [ 0.151885] DOUG: my_pm_clk_suspend, usage=-2 [ 0.151914] DOUG: my_pm_clk_suspend, usage=-2 [ 1.825747] DOUG: my_pm_clk_resume, usage=-1 [ 1.825774] DOUG: my_pm_clk_resume, usage=-1 [ 1.888269] DOUG: my_pm_clk_suspend, usage=-2 [ 1.888282] DOUG: my_pm_clk_suspend, usage=-2 These different patterns have to do with the fact that the core PM Runtime code really isn't designed to be robust to negative usage counts and sometimes may happen to stumble upon a behavior that happens to "work". For instance, you can see that __pm_runtime_suspend() will treat any non-zero value (including negative numbers) as if the device is in use. In any case, let's fix the driver to be correct. We'll hold a pm_runtime reference for the whole probe and then drop it (once!) at the end. We'll get rid of manual pm_runtime_disable() calls in the error handling. We'll also switch to devm_pm_runtime_enable(), which magically handles undoing pm_runtime_use_autosuspend() as of commit b4060db9 ("PM: runtime: Have devm_pm_runtime_enable() handle pm_runtime_dont_use_autosuspend()"). While we're at this, let's also use devm_pm_clk_create() instead of rolling it ourselves. Note that the above changes make it obvious that lpassaudio_create_pm_clks() was doing more than just creating clocks. It was also setting up pm_runtime parameters. Let's rename it. All of these problems were found by code inspection. I started looking at this driver because it was involved in a deadlock that I reported a while ago [1]. Though I bisected the deadlock to commit 1b771839 ("clk: qcom: gdsc: enable optional power domain support"), it was never really clear why that patch affected it other than a luck of timing changes. I'll also note that by fixing the timing (as done in this change) we also seem to aboid the deadlock, which is a nice benefit. Also note that some of the fixes here are much the same type of stuff that Dmitry did in commit 72cfc73f ("clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create"), but I guess lpassaudiocc-sc7280.c didn't exist then. [1] https://lore.kernel.org/r/20220922154354.2486595-1-dianders@chromium.org Fixes: a9dd2663 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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- 15 Nov, 2022 2 commits
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Konrad Dybcio authored
Add support for the display clock controller found on SM6375. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6375 SoC. Signed-off-by:
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- 10 Nov, 2022 2 commits
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Bjorn Andersson authored
The Qualcomm SC8280XP platform has two display clock controller instances, add support for these. Duplication between the two implementations is reduced by reusing any constant data between the two sets of clock data. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP platform has two display clock controllers, add a binding for these. Signed-off-by:
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- 08 Nov, 2022 2 commits
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Krzysztof Kozlowski authored
Clean the Qualcomm SoCs clock bindings: 1. Drop redundant "bindings" in title. 2. Correct language grammar "<independent clause without verb>, which supports" -> "provides". 3. Use full path to the bindings header, so tools can validate it. 4. Drop quotes where not needed. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
Reference common Qualcomm GCC schema to remove common pieces. Signed-off-by:
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- 07 Nov, 2022 4 commits
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Robert Marko authored
Allow passing XO and sleep clocks to the IPQ8074 to avoid having to do a global matching by name. Signed-off-by:
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Robert Marko authored
Convert the IPQ8074 GCC driver to use parent data instead of global name matching. Utilize ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by:
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Melody Olvera authored
Add support for RMPh clocks for QDU1000 and QRU1000 SoCs. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Signed-off-by:
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Melody Olvera authored
Add compatible strings for RPMHCC for QDU1000 and QRU1000. Signed-off-by:
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- 06 Nov, 2022 12 commits
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Robert Foss authored
SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by:
Robert Foss <robert.foss@linaro.org> Reviewed-by:
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Robert Foss authored
SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by:
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Robert Foss authored
Add this previously missing index, since it is supported by the SoCs targeted by the dispcc-sm8250 driver. Signed-off-by:
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Robert Foss authored
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by:
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Robert Foss authored
SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by:
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Manivannan Sadhasivam authored
USB controllers on SM8250 doesn't work after coming back from suspend. This can be fixed by keeping the USB GDSCs in retention mode so that hardware can keep them ON and put into rentention mode once the parent domain goes to a low power state. Fixes: 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
The SM8250 DTS uses three clocks as input to LPASS AudioClock Controller (althopugh Linux driver seems not needing it), so document the missing audio voting clock. Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The SM8250 DTS uses three clocks as input to LPASS AON Clock Controller (althopugh Linux driver seems not needing it), so document the missing audio voting clock. Signed-off-by:
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Krzysztof Kozlowski authored
The SM8250 AON Clock Controller compatible used by Linux driver and DTS is qcom,sm8250-lpass-aoncc. Fixes: 7dbe5a7a ("dt-bindings: clock: Add support for LPASS Always ON Controller") Signed-off-by:
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Krzysztof Kozlowski authored
Convert Qualcomm SDM845 LPASS clock controller bindings to DT schema. Signed-off-by:
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Luca Weiss authored
Convert the text bindings for the lcc to yaml format. Doing this showed that clocks and clock-names were not documented, so fix that now. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Konrad Dybcio authored
Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to ensure set_rate can succeed. Signed-off-by:
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