- 15 Apr, 2013 1 commit
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Sebastian Hesselbarth authored
The common clock api provides some helpers for clk-providers but does not export these helpers. This hinders clk-providers to be built as modules. This patch adds __clk_get_flags() to the list of exported symbols. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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- 14 Apr, 2013 1 commit
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Tony Prisk authored
The case of PLL_TYPE_WM8750 in both these functions is missing a break statement causing a fall-through to the default: case. Insert the missing break statements. Signed-off-by:
Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
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- 12 Apr, 2013 5 commits
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Emilio López authored
This commit uses the new fixed-rate support on the composite clock to unify osc24M_fixed and osc24M clocks, so it matches the actual hardware. Signed-off-by:
Emilio López <emilio@elopez.com.ar> Signed-off-by:
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Mike Turquette authored
The composite clock assumes that any clock implementing the .recalc_rate callback will also implement .round_rate and .set_rate. This is not always true; the basic fixed-rate clock will only implement .recalc_rate and a fixed-divider clock may choose to implement .recalc_rate and .round_rate but not .set_rate. Fix this by conditionally registering .round_rate and .set_rate callbacks based on the rate_ops passed in to clk_composite_register. Signed-off-by:
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Mike Turquette authored
Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by:
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Sebastian Hesselbarth authored
This patch adds a common clock driver for Silicon Labs Si5351a/b/c i2c programmable clock generators. Currently, the driver does not support VXCO feature of si5351b. Passing platform_data or DT bindings selectively allows to overwrite stored Si5351 configuration which is very helpful for clock generators with empty eeprom configuration. Corresponding device tree binding documentation is also added. Signed-off-by:
Daniel Mack <zonque@gmail.com> Acked-by:
Guenter Roeck <linux@roeck-us.net> Tested-by:
Michal Bachraty <michal.bachraty@streamunlimited.com> Signed-off-by:
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Gregory CLEMENT authored
Add support for DT "fixed-factor-clock" binding to the common fixed factor clock support. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by:
Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by:
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- 10 Apr, 2013 3 commits
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Soren Brinkmann authored
Notifiers may return NOTIFY_(OK|DONE|STOP|BAD). The CCF uses an inconsistent mix of checking against NOTIFY_STOP or NOTIFY_BAD. This inconsistency leaves errors undetected in some cases: clk_set_parent() calls __clk_speculate_rates(), which stops when it hits a NOTIFIER_BAD (STOP is ignored), and passes this value back to the caller. clk_set_parent() compares this return value against NOTIFY_STOP only, ignoring NOTIFY_BAD returns. Use NOTIFY_STOP_MASK to detect a negative notifier return value and document all four return value options. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Ulf Hansson authored
The patch setups the first version of the clock tree for ab850x, which is used by u8500 platforms. Mainly sysctrl clocks are used. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Tested-by:
Fabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by:
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Ulf Hansson authored
The abx500 sysctrl clocks are using the ab8500 sysctrl driver to modify the clock hardware. Sysctrl clocks are represented by a ab8500 sysctrl register and with a corresponding bitmask. The sysctrl clocks are slow path clocks, which means clk_prepare and clk_unprepare will be used to gate|ungate these clocks. Signed-off-by:
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- 09 Apr, 2013 4 commits
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Axel Lin authored
cpu_freq_select is used as array subscript, thus the valid value range is 0 ... ARRAY_SIZE() - 1. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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Ulf Hansson authored
Updating the clock tree topology must be protected with the spinlock when doing clk_set_parent, otherwise we can not handle the migration of the enable_count in a safe manner. While issuing the .set_parent callback to make the clk-hw perform the switch to the new parent, we can not hold the spinlock since it is must be allowed to be slow path. This complicates error handling, but is still possible to achieve. Signed-off-by:
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Ulf Hansson authored
Fixup the broken feature of allowing reparent of a clk to the orhpan list and vice verse. When operating on a single-parent clk, the .set_parent callback for the clk hw is optional to implement, but for a multi-parent clk it is mandatory. Moreover improve the errorhandling by verifying the prerequisites before triggering clk notifiers. This will prevent unnecessary rollback with ABORT_RATE_CHANGE. Signed-off-by:
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Ulf Hansson authored
Split __clk_reparent into three pieces, one for doing the actual reparent for updating the clock tree topology, one for the COMMON_CLK_DEBUG code and one for doing the rate recalculation. This patch also makes it possible to hold the spinlock over the update of the clock tree topology, which could not be done before when both debugfs updates and clock rate updates was done within the same function. Signed-off-by:
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- 04 Apr, 2013 3 commits
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Emilio López authored
clk_register will copy this information, so we can just use a normal array and do one less dynamic allocation. Signed-off-by:
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Emilio López authored
This flag was in place to prevent important clocks from getting gated while they had no users. Now that the UART driver supports clocks properly, we can drop this. Signed-off-by:
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Emilio López authored
This patchset adds DT support for all the AXI, AHB, APB0 and APB1 gates present on sunxi SoCs. Signed-off-by:
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- 03 Apr, 2013 2 commits
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Soren Brinkmann authored
Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state, being a divider value of zero. Some hardware implementations allow a zero divider which simply doesn't alter the frequency. I.e. it acts like a divide by one or bypassing the divider. This flag is used to handle such HW in the clk-divider model. Signed-off-by:
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Jean-Francois Moine authored
The use common of_clk_init() function simplifies the clock initialization and adds handling of the DT "fixed-clock". Signed-off-by:
Jean-Francois Moine <moinejf@free.fr> Signed-off-by:
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- 02 Apr, 2013 3 commits
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James Hogan authored
The kerneldoc comment for struct clk_mux documented the non-existent num_clks instead of flags. Correct this. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Mike Turquette authored
Reentrancy into the clock framework is necessary for clock operations that result in nested calls to the clk api. A common example is a clock that is prepared via an i2c transaction, such as a clock inside of a discrete audio chip or a power management IC. The i2c subsystem itself will use the clk api resulting in a deadlock: clk_prepare(audio_clk) i2c_transfer(..) clk_prepare(i2c_controller_clk) The ability to reenter the clock framework prevents this deadlock. Other use cases exist such as allowing .set_rate callbacks to call clk_set_parent to achieve the best rate, or to save power in certain configurations. Yet another example is performing pinctrl operations from a clk_ops callback. Calls into the pinctrl subsystem may call clk_{un}prepare on an unrelated clock. Allowing for nested calls to reenter the clock framework enables both of these use cases. Reentrancy is implemented by two global pointers that track the owner currently holding a global lock. One pointer tracks the owner during sleepable, mutex-protected operations and the other one tracks the owner during non-interruptible, spinlock-protected operations. When the clk framework is entered we try to hold the global lock. If it is held we compare the current task against the current owner; a match implies a nested call and we reenter. If the values do not match then we block on the lock until it is released. Signed-off-by:Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Thomas Gleixner <tglx@linutronix.de> Reviewed-by:
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Mike Turquette authored
Create locking helpers for the global mutex and global spinlock. The definitions of these helpers will be expanded upon in the next patch which introduces reentrancy into the locking scheme. Signed-off-by:
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- 27 Mar, 2013 6 commits
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Michal Simek authored
Include zynq clk header where init function is declared. It removes this sparse warning: drivers/clk/clk-zynq.c:373:13: warning: symbol 'xilinx_zynq_clocks_init' was not declared. Should it be static? Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Emilio López authored
During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by:
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Emilio López authored
This patch contains useful bits of information about the sunxi clocks that may help and/or be interesting for current and future developers. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Emilio López authored
This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: -
Maxime Coquelin authored
In clk_reg_prcmu(), clk->hw.init field is assigned with a reference local to clk_reg_prcmu() function. This patch replaces references to clk->hw.init with calls to __clk_get_name when called after clock registration. This patch applies on top of v3.9-rc4. Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com> Acked-by:
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Fabio Estevam authored
Commit ce4f3313 (clk: add table lookup to mux) caused the following build error on imx_v4_v5_defconfig/imx_v6_v7_defconfig: arch/arm/mach-imx/clk-busy.c:172:11: error: 'struct clk_mux' has no member named 'width' Fix it by passing the 'mask' field. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
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- 26 Mar, 2013 1 commit
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Prashant Gaikwad authored
Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by:
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- 22 Mar, 2013 3 commits
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Peter De Schrijver authored
Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Sachin Kamat authored
Return type of function clk_propagate_rate_change is a pointer. But 0 was being returned. Change it to NULL. Silences the following warning: drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointer Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by:
Pankaj Jangra <jangra.pankaj9@gmail.com> Signed-off-by:
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Wei Yongjun authored
In case of error, the function clk_get() returns ERR_PTR() not NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by:
Barry Song <21cnbao@gmail.com> Signed-off-by:
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- 21 Mar, 2013 2 commits
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Vipul Kumar Samar authored
This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by:
Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by:
Shiraz Hashim <shiraz.hashim@st.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Eduardo Valentin authored
Correcting misspelling inside the clk.txt. Signed-off-by:
Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by:
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- 20 Mar, 2013 1 commit
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Lars-Peter Clausen authored
This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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- 19 Mar, 2013 5 commits
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Ulf Hansson authored
To be able to gate unused prcmu clocks from the clk_disable_unused sequence, clk-prcmu now implements the is_prepared callback. Signed-off-by:
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Ulf Hansson authored
An unprepare_unused callback is introduced due to the same reasons to why the disable_unused callback was added. During the clk_disable_unused sequence, those clk_hw that needs specific treatment with regards to being unprepared, shall implement the unprepare_unused callback. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Ulf Hansson authored
The unused ungated fast clocks are already being disabled from clk_disable_unused at late init. This patch extend this sequence to the slow unused prepared clocks to be unprepared. Unless the optional .is_prepared callback is implemented by a clk_hw the clk_disable_unused sequence will not unprepare any unused clocks, since it will fall back to use the software prepare counter. Signed-off-by:
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Ulf Hansson authored
To reflect whether a clk_hw is prepared the clk_hw may implement the optional is_prepared callback. If not implemented we fall back to use the software prepare counter. Signed-off-by:
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Fabio Estevam authored
Fix the following sparse warnings: drivers/clk/mxs/clk.c:17:1: warning: symbol 'mxs_lock' was not declared. Should it be static? drivers/clk/mxs/clk.c:19:5: warning: symbol 'mxs_clk_wait' was not declared. Should it be static? Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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