- 11 Oct, 2023 9 commits
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Khaled Almahallawy authored
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Fixes: 619a06db ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231005001310.154396-1-khaled.almahallawy@intel.com
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Jani Nikula authored
Structs intel_gvt_irq_info and intel_gvt_irq_map are not used outside of interrupt.c. Hide them, and reduce includes. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230926121904.499888-4-jani.nikula@intel.com
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Jani Nikula authored
struct engine_mmio is not used outside of mmio_context.c. Hide it, and reduce includes. Signed-off-by:
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Jani Nikula authored
intel_gvt_mmio_table.c has no need to include the massive gvt.h. Simplify. Signed-off-by:
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Jani Nikula authored
gvt.h has no need to include i915_drv.h once the unused to_gvt() has been removed. Signed-off-by:
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Vinod Govindapillai authored
Update the number of scalers per pipe based on the display capabilities reported. v1: define the field values instead of the magic number (JaniN) Bspec: 71161 Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231001113155.80659-4-vinod.govindapillai@intel.comSigned-off-by:
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Vinod Govindapillai authored
Update the global dsc flag based on the display capabilities reported. v1: define the field values instead of the magic number (JaniN) Bspec: 71161 Signed-off-by:
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Vinod Govindapillai authored
Register definitions to track the reported scalable display feature configurations Bspec: 71161 Signed-off-by:
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Chaitanya Kumar Borah authored
Add a wrapper around intel_step_name that takes in driver data as an argument. This wrapper will help maintain compatibility with the proposed xe driver. Signed-off-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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- 10 Oct, 2023 2 commits
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Suraj Kandpal authored
Free hw_crtc_state in verify_crtc_state after we are done using this or else it's just a resource leak. Fixes: 2745bdda ("drm/i915: Stop clobbering old crtc state during state check") Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
VLV was missed when the color.get_config() hook was added. Remedy that. Not really sure what the final plan here was since a bunch of color related readout was left in intel_display.c anyway, but that's for anothr day to figure out... Cc: Jani Nikula <jani.nikula@intel.com> Fixes: 9af09dfc ("drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color") Signed-off-by:
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- 09 Oct, 2023 1 commit
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Randy Dunlap authored
Correct typo of "its". Add commas for clarity. Capitalize L3. Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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- 07 Oct, 2023 1 commit
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Suraj Kandpal authored
Remove redundant intel_connector NULL check. Having it here just creates further confusion and also the variable already gets dereferenced before the aforementioned NULL check Signed-off-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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- 06 Oct, 2023 12 commits
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Ville Syrjälä authored
Switch the state checker over to using the new 'i915' variable name insteda of the old 'dev_priv'. Signed-off-by:
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Ville Syrjälä authored
Switch over to the modern variable naming in the state checker. Ie. rename the pipe_config stuff to crtc_state. Also make it clear which is the "software state" (ie. what the current state should be) vs. "hardware state" (ie. what the currnet state really is). Signed-off-by:
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Ville Syrjälä authored
We're passing in a totally random mismash of things into the state checker. Clean it up to pass in the minimum needed. Signed-off-by:
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Ville Syrjälä authored
Mark the remaining crtc states used by the state checker as const. There is no reason to ever mutate them here. Signed-off-by:
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Ville Syrjälä authored
Passing in the atomic state + crtc state is a bit weird. The latter can be just the crtc (which is the normal calling convention used in a lot of other places). Signed-off-by:
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Ville Syrjälä authored
State checkers should never modify the crtc states, so make them const. Signed-off-by:
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Ville Syrjälä authored
There is never any reason to pass in both the crtc and its state as one can always dig out the crtc from its state. But for more consistency across the whole state checker let's just pass the overall atomic state+crtc here as well. v2: Also pass state+crtc here (Jani) Reviewed-by:
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Ville Syrjälä authored
The skl+ wm state checker has no reason to modify the crtc state, so make it const. Signed-off-by:
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Ville Syrjälä authored
Make life simpler by just passing in the atomic state + crtc instead of plumbing in all kinds of crtc states. Signed-off-by:
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Ville Syrjälä authored
The DPLL state checker should not be modifying the crtc states, so make the const. Signed-off-by:
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Ville Syrjälä authored
The state checker overwrites the old crtc state with the current hardware state. While that does save a kmalloc() it seems rather dubious as there might still be something that we need in the old crtc state. Stop doing that and just allocate a temporary state for the state checker. Should the extra malloc during the commit phase turn out too annoying we could of course preallocate one for each crtc, but let's proceed with the straightforward approch for now. And while at it let's mark the new crtc state as const to make sure the state checker doesn't mess it up. Signed-off-by:
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Ville Syrjälä authored
intel_psr_pre_plane_update() operates on a per-crtc level, whereas intel_psr_post_plane_update() operates on the whole atomic commit, for no real reason that I can see. Adjust intel_psr_post_plane_update() to match the intel_psr_pre_plane_update() approach. Signed-off-by:
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- 05 Oct, 2023 8 commits
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Ville Syrjälä authored
Plane stride is always a multiple of 64 bytes. Remove the pointless check that really doesn't have anything to do with FBC. Signed-off-by:
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Ville Syrjälä authored
Carve up pixel_format_is_valid() into per-platform variants to make it easier to see what limits are actually being imposed. Note that the XRGB1555 can be dropped from the g4x+ variant since the plane no longer supports that format anyway. TODO: maybe go for vfuncs later v2: Update for lnl changes Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> #v1 Reviewed-by:
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Ville Syrjälä authored
Carve up rotation_is_valid() into per-platform variants to make it easier to see what limits are actually being imposed. TODO: maybe go for vfuncs later Reviewed-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
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Ville Syrjälä authored
Carve up tiling_is_valid() into per-platform variants to make it easier to see what limits are actually being imposed. TODO: maybe go for vfuncs later Reviewed-by:
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Ville Syrjälä authored
Carve up stride_is_valid() into per-platform variants to make it easier to see what limits are actually being imposed. TODO: maybe go for vfuncs later Reviewed-by:
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Ville Syrjälä authored
The 16k max plane stride limit seems to be originally from i965gm, and no explicit limit has been specified since (g4x+). So let's assume the max plane stride itself is a suitable limit also for the more recent FBC hardware. In fact even for i965gm the max X-tiled stride is also 16k so technically we don't need the check there either, but let's keep it there anyway since it's explicitly mentioned in the spec. Gen2/3 have more strict limits checked separately. Reviewed-by:
Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
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Uros Bizjak authored
Use local64_try_cmpxchg instead of local64_cmpxchg (*ptr, old, new) == old in i915_pmu_event_read. x86 CMPXCHG instruction returns success in ZF flag, so this change saves a compare after cmpxchg (and related move instruction in front of cmpxchg). Also, try_cmpxchg implicitly assigns old *ptr value to "old" when cmpxchg fails. There is no need to re-read the value in the loop. No functional change intended. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
Uros Bizjak <ubizjak@gmail.com> Reviewed-by:
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Uma Shankar authored
Current vga arbiter implementation in i915 needs a re-design. The current approach would cause real problems if anyone actually needs to talk another GPU using legacy VGA resources. The main issue is that X becomes a slideshow if it thinks there are multiple GPUs that have VGA decoding enabled as it insists on adjusting the VGA routing pretty much for every little operation involving any of the GPUs. The cleanup will be planned for i915. Meanwhile to focus on Xe upstreaming and have a cleaner separation, the said functionality is being moved to a different file exclusive for i915. Xe driver will re-use rest of the display code from i915. v2: Addressed Jani Nikula's review comments. v3: Dropped a duplicate function (Jani) v4: Updated commit message with reasoning as sugested by Ville. Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230929074306.1533859-1-uma.shankar@intel.com
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- 04 Oct, 2023 7 commits
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Imre Deak authored
Atm the MST encoder config computation may use an out-of-date pbn_div value, if the sink is unplugged and a sink is replugged with different link rate/lane count capabilities. The current way of reinitializing pbn_div depends on pbn_div getting cleared via intel_atomic_check() -> drm_dp_mst_atomic_check() -> drm_dp_mst_atomic_check_payload_alloc_limits(), however the clearing won't happen if the sink got unplugged (and hence drm_dp_mst_topology_mgr::mst_state being false). To fix the above, simply update pbn_div unconditionally during config computation, making pbn_div always match the link rate and lane count. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230929154929.343947-1-imre.deak@intel.com
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Niko Tsirakis authored
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled", followed by link training errors. Intel engineers recommended increasing this timeout and that does resolve the issue. On some CometLake-based device designs the Parade PS175 takes more than 400ms to settle in PCON mode. 100 reboot trials on one device resulted in a median settle time of 440ms and a maximum of 444ms. Even after increasing the timeout to 500ms, 2% of devices still had this error. So this increases the timeout to 800ms. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9443Signed-off-by:
Pablo Ceballos <pceballos@google.com> Signed-off-by:
Niko Tsirakis <ntsirakis@google.com> Reviewed-by:
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Jani Nikula authored
Since gt0 == i915->gt[0], just drop the former. Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5319364f4c9416fed218382d020a57c5b0a17bee.1696236329.git.jani.nikula@intel.com
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Jani Nikula authored
Convert i915->gt0 to a pointer, and allocate it dynamically. Signed-off-by:
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Jani Nikula authored
Have to give up the const on i915 pointer, but it's not big of a deal considering non-const i915 gets passed all over the place. Signed-off-by:
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Jani Nikula authored
Backmerge to sync up with drm-intel-gt-next and drm-misc-next. Signed-off-by: -
Ville Syrjälä authored
Do a s/dev_priv/i915/ pass over the shared_dpll code to get the variable names into sync with modern standards. v2: Rebase Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by:
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