1. 05 Jun, 2024 6 commits
    • Linus Torvalds's avatar
      Merge tag 'i2c-for-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux · 558dc49a
      Linus Torvalds authored
      Pull i2c fixes from Wolfram Sang:
       "This should have been my second pull request during the merge window
        but one dependency in the drm subsystem fell through the cracks and
        was only applied for rc2.
      
        Now we can finally remove I2C_CLASS_SPD"
      
      * tag 'i2c-for-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
        i2c: Remove I2C_CLASS_SPD
        i2c: synquacer: Remove a clk reference from struct synquacer_i2c
      558dc49a
    • Linus Torvalds's avatar
      Merge tag 'tpmdd-next-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd · 208d9b65
      Linus Torvalds authored
      Pull tpm fixes from Jarkko Sakkinen:
       "The bug fix for tpm_tis_core_init() is not that critical but still
        makes sense to get into release for the sake of better quality.
      
        I included the Intel CPU model define change mainly to help Tony just
        a bit, as for this subsystem it cannot realistically speaking cause
        any possible harm"
      
      * tag 'tpmdd-next-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd:
        tpm: Switch to new Intel CPU model defines
        tpm_tis: Do *not* flush uninitialized work
      208d9b65
    • Linus Torvalds's avatar
      Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm · 71d7b52c
      Linus Torvalds authored
      Pull kvm fixes from Paolo Bonzini:
       "This is dominated by a couple large series for ARM and x86
        respectively, but apart from that things are calm.
      
        ARM:
      
         - Large set of FP/SVE fixes for pKVM, addressing the fallout from the
           per-CPU data rework and making sure that the host is not involved
           in the FP/SVE switching any more
      
         - Allow FEAT_BTI to be enabled with NV now that FEAT_PAUTH is
           completely supported
      
         - Fix for the respective priorities of Failed PAC, Illegal Execution
           state and Instruction Abort exceptions
      
         - Fix the handling of AArch32 instruction traps failing their
           condition code, which was broken by the introduction of
           ESR_EL2.ISS2
      
         - Allow vcpus running in AArch32 state to be restored in System mode
      
         - Fix AArch32 GPR restore that would lose the 64 bit state under some
           conditions
      
        RISC-V:
      
         - No need to use mask when hart-index-bits is 0
      
         - Fix incorrect reg_subtype labels in
           kvm_riscv_vcpu_set_reg_isa_ext()
      
        x86:
      
         - Fixes and debugging help for the #VE sanity check.
      
           Also disable it by default, even for CONFIG_DEBUG_KERNEL, because
           it was found to trigger spuriously (most likely a processor erratum
           as the exact symptoms vary by generation).
      
         - Avoid WARN() when two NMIs arrive simultaneously during an
           NMI-disabled situation (GIF=0 or interrupt shadow) when the
           processor supports virtual NMI.
      
           While generally KVM will not request an NMI window when virtual
           NMIs are supported, in this case it *does* have to single-step over
           the interrupt shadow or enable the STGI intercept, in order to
           deliver the latched second NMI.
      
         - Drop support for hand tuning APIC timer advancement from userspace.
      
           Since we have adaptive tuning, and it has proved to work well, drop
           the module parameter for manual configuration and with it a few
           stupid bugs that it had"
      
      * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (32 commits)
        KVM: x86/mmu: Don't save mmu_invalidate_seq after checking private attr
        KVM: arm64: Ensure that SME controls are disabled in protected mode
        KVM: arm64: Refactor CPACR trap bit setting/clearing to use ELx format
        KVM: arm64: Consolidate initializing the host data's fpsimd_state/sve in pKVM
        KVM: arm64: Eagerly restore host fpsimd/sve state in pKVM
        KVM: arm64: Allocate memory mapped at hyp for host sve state in pKVM
        KVM: arm64: Specialize handling of host fpsimd state on trap
        KVM: arm64: Abstract set/clear of CPTR_EL2 bits behind helper
        KVM: arm64: Fix prototype for __sve_save_state/__sve_restore_state
        KVM: arm64: Reintroduce __sve_save_state
        KVM: x86: Drop support for hand tuning APIC timer advancement from userspace
        KVM: SEV-ES: Delegate LBR virtualization to the processor
        KVM: SEV-ES: Disallow SEV-ES guests when X86_FEATURE_LBRV is absent
        KVM: SEV-ES: Prevent MSR access post VMSA encryption
        RISC-V: KVM: Fix incorrect reg_subtype labels in kvm_riscv_vcpu_set_reg_isa_ext function
        RISC-V: KVM: No need to use mask when hart-index-bit is 0
        KVM: arm64: nv: Expose BTI and CSV_frac to a guest hypervisor
        KVM: arm64: nv: Fix relative priorities of exceptions generated by ERETAx
        KVM: arm64: AArch32: Fix spurious trapping of conditional instructions
        KVM: arm64: Allow AArch32 PSTATE.M to be restored as System mode
        ...
      71d7b52c
    • Tao Su's avatar
      KVM: x86/mmu: Don't save mmu_invalidate_seq after checking private attr · db574f2f
      Tao Su authored
      Drop the second snapshot of mmu_invalidate_seq in kvm_faultin_pfn().
      Before checking the mismatch of private vs. shared, mmu_invalidate_seq is
      saved to fault->mmu_seq, which can be used to detect an invalidation
      related to the gfn occurred, i.e. KVM will not install a mapping in page
      table if fault->mmu_seq != mmu_invalidate_seq.
      
      Currently there is a second snapshot of mmu_invalidate_seq, which may not
      be same as the first snapshot in kvm_faultin_pfn(), i.e. the gfn attribute
      may be changed between the two snapshots, but the gfn may be mapped in
      page table without hindrance. Therefore, drop the second snapshot as it
      has no obvious benefits.
      
      Fixes: f6adeae8 ("KVM: x86/mmu: Handle no-slot faults at the beginning of kvm_faultin_pfn()")
      Signed-off-by: default avatarTao Su <tao1.su@linux.intel.com>
      Message-ID: <20240528102234.2162763-1-tao1.su@linux.intel.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      db574f2f
    • Paolo Bonzini's avatar
      Merge tag 'kvmarm-fixes-6.10-1' of... · 45ce0314
      Paolo Bonzini authored
      Merge tag 'kvmarm-fixes-6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
      
      KVM/arm64 fixes for 6.10, take #1
      
      - Large set of FP/SVE fixes for pKVM, addressing the fallout
        from the per-CPU data rework and making sure that the host
        is not involved in the FP/SVE switching any more
      
      - Allow FEAT_BTI to be enabled with NV now that FEAT_PAUTH
        is copletely supported
      
      - Fix for the respective priorities of Failed PAC, Illegal
        Execution state and Instruction Abort exceptions
      
      - Fix the handling of AArch32 instruction traps failing their
        condition code, which was broken by the introduction of
        ESR_EL2.ISS2
      
      - Allow vpcus running in AArch32 state to be restored in
        System mode
      
      - Fix AArch32 GPR restore that would lose the 64 bit state
        under some conditions
      45ce0314
    • Tony Luck's avatar
      tpm: Switch to new Intel CPU model defines · f071d02e
      Tony Luck authored
      New CPU #defines encode vendor and family as well as model.
      
      Link: https://lore.kernel.org/all/20240520224620.9480-4-tony.luck@intel.com/Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      Reviewed-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
      Signed-off-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
      f071d02e
  2. 04 Jun, 2024 12 commits
  3. 03 Jun, 2024 15 commits
    • Linus Torvalds's avatar
      Merge tag 'cxl-fixes-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl · 2ab79514
      Linus Torvalds authored
      Pull cxl fixes from Dave Jiang:
      
       - Compile fix for cxl-test from missing linux/vmalloc.h
      
       - Fix for memregion leaks in devm_cxl_add_region()
      
      * tag 'cxl-fixes-6.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
        cxl/region: Fix memregion leaks in devm_cxl_add_region()
        cxl/test: Add missing vmalloc.h for tools/testing/cxl/test/mem.c
      2ab79514
    • Paolo Bonzini's avatar
      Merge tag 'kvm-riscv-fixes-6.10-1' of https://github.com/kvm-riscv/linux into HEAD · b50788f7
      Paolo Bonzini authored
      KVM/riscv fixes for 6.10, take #1
      
      - No need to use mask when hart-index-bits is 0
      - Fix incorrect reg_subtype labels in kvm_riscv_vcpu_set_reg_isa_ext()
      b50788f7
    • Paolo Bonzini's avatar
      Merge branch 'kvm-fixes-6.10-1' into HEAD · b3233c73
      Paolo Bonzini authored
      * Fixes and debugging help for the #VE sanity check.  Also disable
        it by default, even for CONFIG_DEBUG_KERNEL, because it was found
        to trigger spuriously (most likely a processor erratum as the
        exact symptoms vary by generation).
      
      * Avoid WARN() when two NMIs arrive simultaneously during an NMI-disabled
        situation (GIF=0 or interrupt shadow) when the processor supports
        virtual NMI.  While generally KVM will not request an NMI window
        when virtual NMIs are supported, in this case it *does* have to
        single-step over the interrupt shadow or enable the STGI intercept,
        in order to deliver the latched second NMI.
      
      * Drop support for hand tuning APIC timer advancement from userspace.
        Since we have adaptive tuning, and it has proved to work well,
        drop the module parameter for manual configuration and with it a
        few stupid bugs that it had.
      b3233c73
    • Sean Christopherson's avatar
      KVM: x86: Drop support for hand tuning APIC timer advancement from userspace · 89a58812
      Sean Christopherson authored
      Remove support for specifying a static local APIC timer advancement value,
      and instead present a read-only boolean parameter to let userspace enable
      or disable KVM's dynamic APIC timer advancement.  Realistically, it's all
      but impossible for userspace to specify an advancement that is more
      precise than what KVM's adaptive tuning can provide.  E.g. a static value
      needs to be tuned for the exact hardware and kernel, and if KVM is using
      hrtimers, likely requires additional tuning for the exact configuration of
      the entire system.
      
      Dropping support for a userspace provided value also fixes several flaws
      in the interface.  E.g. KVM interprets a negative value other than -1 as a
      large advancement, toggling between a negative and positive value yields
      unpredictable behavior as vCPUs will switch from dynamic to static
      advancement, changing the advancement in the middle of VM creation can
      result in different values for vCPUs within a VM, etc.  Those flaws are
      mostly fixable, but there's almost no justification for taking on yet more
      complexity (it's minimal complexity, but still non-zero).
      
      The only arguments against using KVM's adaptive tuning is if a setup needs
      a higher maximum, or if the adjustments are too reactive, but those are
      arguments for letting userspace control the absolute max advancement and
      the granularity of each adjustment, e.g. similar to how KVM provides knobs
      for halt polling.
      
      Link: https://lore.kernel.org/all/20240520115334.852510-1-zhoushuling@huawei.com
      Cc: Shuling Zhou <zhoushuling@huawei.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
      Message-ID: <20240522010304.1650603-1-seanjc@google.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      89a58812
    • Ravi Bangoria's avatar
      KVM: SEV-ES: Delegate LBR virtualization to the processor · b7e4be0a
      Ravi Bangoria authored
      As documented in APM[1], LBR Virtualization must be enabled for SEV-ES
      guests. Although KVM currently enforces LBRV for SEV-ES guests, there
      are multiple issues with it:
      
      o MSR_IA32_DEBUGCTLMSR is still intercepted. Since MSR_IA32_DEBUGCTLMSR
        interception is used to dynamically toggle LBRV for performance reasons,
        this can be fatal for SEV-ES guests. For ex SEV-ES guest on Zen3:
      
        [guest ~]# wrmsr 0x1d9 0x4
        KVM: entry failed, hardware error 0xffffffff
        EAX=00000004 EBX=00000000 ECX=000001d9 EDX=00000000
      
        Fix this by never intercepting MSR_IA32_DEBUGCTLMSR for SEV-ES guests.
        No additional save/restore logic is required since MSR_IA32_DEBUGCTLMSR
        is of swap type A.
      
      o KVM will disable LBRV if userspace sets MSR_IA32_DEBUGCTLMSR before the
        VMSA is encrypted. Fix this by moving LBRV enablement code post VMSA
        encryption.
      
      [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June
           2023, Vol 2, 15.35.2 Enabling SEV-ES.
           https://bugzilla.kernel.org/attachment.cgi?id=304653
      
      Fixes: 376c6d28 ("KVM: SVM: Provide support for SEV-ES vCPU creation/loading")
      Co-developed-by: default avatarNikunj A Dadhania <nikunj@amd.com>
      Signed-off-by: default avatarNikunj A Dadhania <nikunj@amd.com>
      Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
      Message-ID: <20240531044644.768-4-ravi.bangoria@amd.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b7e4be0a
    • Ravi Bangoria's avatar
      KVM: SEV-ES: Disallow SEV-ES guests when X86_FEATURE_LBRV is absent · d9220562
      Ravi Bangoria authored
      As documented in APM[1], LBR Virtualization must be enabled for SEV-ES
      guests. So, prevent SEV-ES guests when LBRV support is missing.
      
      [1]: AMD64 Architecture Programmer's Manual Pub. 40332, Rev. 4.07 - June
           2023, Vol 2, 15.35.2 Enabling SEV-ES.
           https://bugzilla.kernel.org/attachment.cgi?id=304653
      
      Fixes: 376c6d28 ("KVM: SVM: Provide support for SEV-ES vCPU creation/loading")
      Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
      Message-ID: <20240531044644.768-3-ravi.bangoria@amd.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      d9220562
    • Nikunj A Dadhania's avatar
      KVM: SEV-ES: Prevent MSR access post VMSA encryption · 27bd5fdc
      Nikunj A Dadhania authored
      KVM currently allows userspace to read/write MSRs even after the VMSA is
      encrypted. This can cause unintentional issues if MSR access has side-
      effects. For ex, while migrating a guest, userspace could attempt to
      migrate MSR_IA32_DEBUGCTLMSR and end up unintentionally disabling LBRV on
      the target. Fix this by preventing access to those MSRs which are context
      switched via the VMSA, once the VMSA is encrypted.
      Suggested-by: default avatarSean Christopherson <seanjc@google.com>
      Signed-off-by: default avatarNikunj A Dadhania <nikunj@amd.com>
      Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
      Message-ID: <20240531044644.768-2-ravi.bangoria@amd.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      27bd5fdc
    • Linus Torvalds's avatar
      Merge tag 'loongarch-fixes-6.10-1' of... · f06ce441
      Linus Torvalds authored
      Merge tag 'loongarch-fixes-6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
      
      Pull LoongArch fixes from Huacai Chen:
       "Some bootloader interface fixes, a dts fix, and a trivial cleanup"
      
      * tag 'loongarch-fixes-6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
        LoongArch: Fix GMAC's phy-mode definitions in dts
        LoongArch: Override higher address bits in JUMP_VIRT_ADDR
        LoongArch: Fix entry point in kernel image header
        LoongArch: Add all CPUs enabled by fdt to NUMA node 0
        LoongArch: Fix built-in DTB detection
        LoongArch: Remove CONFIG_ACPI_TABLE_UPGRADE in platform_init()
      f06ce441
    • Huacai Chen's avatar
      LoongArch: Fix GMAC's phy-mode definitions in dts · eb36e520
      Huacai Chen authored
      The GMAC of Loongson chips cannot insert the correct 1.5-2ns delay. So
      we need the PHY to insert internal delays for both transmit and receive
      data lines from/to the PHY device. Fix this by changing the "phy-mode"
      from "rgmii" to "rgmii-id" in dts.
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      eb36e520
    • Jiaxun Yang's avatar
      LoongArch: Override higher address bits in JUMP_VIRT_ADDR · 1098efd2
      Jiaxun Yang authored
      In JUMP_VIRT_ADDR we are performing an or calculation on address value
      directly from pcaddi.
      
      This will only work if we are currently running from direct 1:1 mapping
      addresses or firmware's DMW is configured exactly same as kernel. Still,
      we should not rely on such assumption.
      
      Fix by overriding higher bits in address comes from pcaddi, so we can
      get rid of or operator.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      1098efd2
    • Jiaxun Yang's avatar
      LoongArch: Fix entry point in kernel image header · beb28000
      Jiaxun Yang authored
      Currently kernel entry in head.S is in DMW address range, firmware is
      instructed to jump to this address after loading the kernel image.
      
      However kernel should not make any assumption on firmware's DMW
      setting, thus the entry point should be a physical address falls into
      direct translation region.
      
      Fix by converting entry address to physical and amend entry calculation
      logic in libstub accordingly.
      
      BTW, use ABSOLUTE() to calculate variables to make Clang/LLVM happy.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      beb28000
    • Jiaxun Yang's avatar
      LoongArch: Add all CPUs enabled by fdt to NUMA node 0 · 3de9c42d
      Jiaxun Yang authored
      NUMA enabled kernel on FDT based machine fails to boot because CPUs
      are all in NUMA_NO_NODE and mm subsystem won't accept that.
      
      Fix by adding them to default NUMA node at FDT parsing phase and move
      numa_add_cpu(0) to a later point.
      
      Cc: stable@vger.kernel.org
      Fixes: 88d4d957 ("LoongArch: Add FDT booting support from efi system table")
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      3de9c42d
    • Jiaxun Yang's avatar
      LoongArch: Fix built-in DTB detection · b56f67a6
      Jiaxun Yang authored
      fdt_check_header(__dtb_start) will always success because kernel
      provides a dummy dtb, and by coincidence __dtb_start clashed with
      entry of this dummy dtb. The consequence is fdt passed from firmware
      will never be taken.
      
      Fix by trying to utilise __dtb_start only when CONFIG_BUILTIN_DTB is
      enabled.
      
      Cc: stable@vger.kernel.org
      Fixes: 7b937cc2 ("of: Create of_root if no dtb provided by firmware")
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      b56f67a6
    • Tiezhu Yang's avatar
      LoongArch: Remove CONFIG_ACPI_TABLE_UPGRADE in platform_init() · 6c3ca665
      Tiezhu Yang authored
      Both acpi_table_upgrade() and acpi_boot_table_init() are defined as
      empty functions under !CONFIG_ACPI_TABLE_UPGRADE and !CONFIG_ACPI in
      include/linux/acpi.h, there are no implicit declaration errors with
      various configs.
      
        #ifdef CONFIG_ACPI_TABLE_UPGRADE
        void acpi_table_upgrade(void);
        #else
        static inline void acpi_table_upgrade(void) { }
        #endif
      
        #ifdef	CONFIG_ACPI
        ...
        void acpi_boot_table_init (void);
        ...
        #else	/* !CONFIG_ACPI */
        ...
        static inline void acpi_boot_table_init(void)
        {
        }
        ...
        #endif	/* !CONFIG_ACPI */
      
      As Huacai suggested, CONFIG_ACPI_TABLE_UPGRADE is ugly and not necessary
      here, just remove it. At the same time, just keep CONFIG_ACPI to prevent
      potential build errors in future, and give a signal to indicate the code
      is ACPI-specific. For the same reason, we also put acpi_table_upgrade()
      under CONFIG_ACPI.
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      6c3ca665
    • Wolfram Sang's avatar
      Merge tag 'i2c-host-6.10-pt2' of... · c4aff1d1
      Wolfram Sang authored
      Merge tag 'i2c-host-6.10-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-current
      
      Removed the SPD class of i2c devices from the device core.
      
      Additionally, a cleanup in the Synquacer code removes the pclk
      from the global structure, as it is used only in the probe.
      Therefore, it is now declared locally.
      c4aff1d1
  4. 02 Jun, 2024 7 commits