This patch adds support for SATA on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch adds support for GPMI-NAND on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch adds support for USB_HOST on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch adds support for USB_OTG on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh <ashutosh.s@phytec.in>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

On imx6sl-evk board the VGEN1 regulator powers up the NVCC_1P2V domain of the
imx6sl SoC, so we need to keep it always powered.

According to imx6sl datasheet the GPIO block has three supplies:
NVCC33_IO, NVCC18_IO and NVCC_1P2V and it states that:
"All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions
whether the associated I/O pins are in use or not"

This problem has been observed by the fact that a GPIO connected to an LED could
not work when the PMIC driver was enabled.

Keeping VGEN1 regulator always enabled fixes the problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The D9 LED controlled by gpio on the imx6qdl-sabreauto
CPU board is a debug LED according to the board design.
This patch adds the relevant device tree nodes to the
imx6qdl-sabreauto device tree file to support this LED.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

According to datasheet, i.MX6Q has setpoint of 852MHz
which is exclusive with 996MHz, the fuse map of speed_grading
defines the max speed of ARM, here we add this 852MHz
setpoint opp info, kernel will check the speed_grading
fuse and remove all illegal setpoints.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Apply the same work-around for i.MX 6D/Q erratum 006687 as used for
Sabre Lite for the Wandboard Dual / Quad.

Like on the Sabre Lite, GPIO6 is used as a power down output for
camera expansion boards. However, these expansion boards do not work
with mainline yet anyway.

Tested on a Wandboard Quad. Before the patch:

root@arm:~# ping -q -f -c 10000 192.168.2.1
PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data.

=== 192.168.2.1 ping statistics ===
10000 packets transmitted, 10000 received, 0% packet loss, time 97363ms
rtt min/avg/max/mdev = 0.290/9.586/10.198/1.432 ms, pipe 2, ipg/ewma 9.737/9.672 ms

After the patch:

root@arm:~# ping -q -f -c 10000 192.168.2.1
PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data.

=== 192.168.2.1 ping statistics ===
10000 packets transmitted, 10000 received, 0% packet loss, time 4810ms
rtt min/avg/max/mdev = 0.246/0.355/0.863/0.044 ms, ipg/ewma 0.481/0.319 ms
Signed-off-by: Sascha Silbe <x-linux@infra-silbe.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

GPIO3_20 is connected to a debug LED.

Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

mx6 sabreauto boards have Freescale PFUZE100 regulator, so add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

imx6sl-evk has a wm8962 codec. Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

imx6sl-evk board has Freescale PFUZE100 regulator, so add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add support for the GK802 'QUAD CORE Mini PC', which seems to be loosely
based on the Freescale i.MX6Q HDMI dongle reference design.
It is supposedly identical to the Hiapad Hi802.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The DFI FS700-M60 is a q7 board with i.MX6 quad, dual, duallite or solo
SoC. This adds support for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

The quad version has a SPI controller more than the other
versions. Add an alias for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add LVDS support for mx6 sabreauto boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

i.MX6SL EVK board has a 3*3 keypad matrix to support 8 keypads,
enable them, the keymap is as below:

SW6:  MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
SW7:  MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
SW8:  MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
SW9:  MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
SW10: MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
SW11: MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
SW12: MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
SW13: MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add ocram device support on i.MX6SL.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Enable dma support for espci controller
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

mx6 sabresd boards have Freescale PFUZE100 regulator, so add support for it.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add anatop phandle for usbphy
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This works around a hardware bug.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This works around a hardware bug.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This works around a hardware bug.
From "Chip Errata for the i.MX 6Dual/6Quad"

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.

The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.

Before this patch, ping times of a Sabre Lite board are quite
random:
ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=15.7 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=14.4 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=13.4 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=12.4 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=11.4 ms

=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 2004ms
rtt min/avg/max/mdev = 11.431/13.501/15.746/1.508 ms
____________________________________________________
After this patch:

ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=0.120 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=0.175 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=0.169 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=0.168 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=0.172 ms

=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 1999ms
rtt min/avg/max/mdev = 0.120/0.160/0.175/0.026 ms
____________________________________________________

Also, apply same change to imx6qdl-nitrogen6x.

This change may not be appropriate for all boards.
Sabre Lite uses GPIO6 as a power down output for a ov5642
camera. As this expansion board does not yet work with mainline,
this is not yet a conflict. It would be nice to have an alternative
fix for boards where this is a problem.

For example Sabre SD uses GPIO6 for I2C3_SDA. It also
has long ping times currently. But cannot use this fix
without giving up a touchscreen.

Its ping times are also random.

ping 192.168.0.19 -i.5 -c5
PING 192.168.0.19 (192.168.0.19) 56(84) bytes of data.
64 bytes from 192.168.0.19: icmp_req=1 ttl=64 time=16.0 ms
64 bytes from 192.168.0.19: icmp_req=2 ttl=64 time=15.4 ms
64 bytes from 192.168.0.19: icmp_req=3 ttl=64 time=14.4 ms
64 bytes from 192.168.0.19: icmp_req=4 ttl=64 time=13.4 ms
64 bytes from 192.168.0.19: icmp_req=5 ttl=64 time=12.4 ms

=== 192.168.0.19 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 2003ms
rtt min/avg/max/mdev = 12.451/14.369/16.057/1.316 ms
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

We need to be able to override interrupts in board file to
workaround a hardware bug for ethernet interrupts
waking the processor by using interrupts-extended.
So, use interrupts-extended here as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

From "Chip Errata for the i.MX 6Dual/6Quad"

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.

The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.

Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
workaround this problem.

The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
The mux reg value is 0x11, so that the observable mux is routed to
this pin and to the gpio controller(sion bit). These magic values
come from Ranjani Vaidyanathan's patch:
"ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active"
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Note that the fec driver code currently hard-codes an active-low
reset, regardless of the flags in the device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Instead of calling the regulator for the ARM core as 'cpu', let's rename it
as 'vddarm', so that we keep a better consistency with the other internal
regulators:

vdd1p1: 800 <--> 1375 mV at 1100 mV
vdd3p0: 2800 <--> 3150 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2400 mV
vddarm: 725 <--> 1450 mV at 1150 mV
vddpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1200 mV
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch adds support for imx6qdl-sabresd board's power
key, the key is named "SW1" on board, press it can wake up
system from suspend.

Add a new pinctrl entry for gpio keys and move all gpio
keys pin to this entry.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Device tree for iMX6SL doesn't have an existing cpu frequency table
as well as the VDDSOC/PU.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Thermal sensor needs pll3_usb_otg when measuring temperature,
so we need to pass clk info to thermal driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

This patch adds cpufreq dts for i.mx6dl to support cpufreq driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info from dts together.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP
by more than 200mV, as all of i.MX6Q boards' VDD_CACHE_CAP currently
are connected to VDDSOC_CAP, so we need to follow this rule by
increasing VDDARM_CAP's voltage.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add power, menu, home, back, volume up, and volume down
buttons.

Also, apply same changes to imx6qdl-nitrogen6x.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Add file imx6q-nitrogen6x.dts,
	imx6dl-nitrogen6x.dts,
	imx6qdl-nitrogen6x.dtsi

And add board to makefile.

Eric Nelson created a web page to show the
differences between Nitrogen6x and Sabre Lite boards.
http://boundarydevices.com/differences-sabre-lite-nitrogen6xSigned-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>