- 17 Sep, 2020 25 commits
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Luben Tuikov authored
Not being able to create amdgpu sysfs attributes is not a fatal error warranting not to continue to try to bring up the display. Thus, if we get an error trying to create amdgpu sysfs attrs, report it and continue on to try to bring up a display. Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Acked-by:
Slava Abramov <slava.abramov@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiansong Chen authored
The firmware provided via MODULE_FIRMWARE appears in the module information. External tools(eg. dracut) may use the list of fw files to include them as appropriate in an initramfs, thus missing declaration will lead to request firmware failure in boot time. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Signed-off-by:
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Shirish S authored
With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set appropriately the system hangs without any trace during S3. To ease debug and to ensure that the failure, if any, was caused by a race conditions that disabled write access to SDPIF_MMIO_CNTRL_0 register, warn the user about it. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Evan Quan authored
Update the UMD stable Pstate settings with correct clocks. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Evan Quan authored
SMU FCLK,SOCCLK have dependency on VCN CLKs. Lower VCN values so that FCLK, SOCCLK reflect values set by UMD Stable Pstate. Signed-off-by:
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Evan Quan authored
Since that should be the correct place to put ASIC specific workarounds. Signed-off-by:
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Evan Quan authored
If dc reported by gpio is supported, the power source switching will be performed by pmfw automatically. Thus the power source setting workaround for Navi1x will be not needed. Signed-off-by:
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Evan Quan authored
Process any pending interrupt that occured before driver register for interrupt from GPIO/SMU. Signed-off-by:
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Evan Quan authored
Which tells it's a normal pstate change or memory retraining. Signed-off-by:
Changfeng Zhu <Changfeng.Zhu@amd.com> Acked-by:
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Evan Quan authored
Which tells it's a normal pstate change or memory retraining. Signed-off-by:
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Evan Quan authored
The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Signed-off-by:
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Evan Quan authored
Raven never goes to swsmu path. So "adev->smu.ppt_funcs" will be always false. Signed-off-by:
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Evan Quan authored
Drop unneeded "ret". Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Evan Quan authored
Either this was already performed in parent API. Or the table is confirmed to exist. Signed-off-by:
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Evan Quan authored
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by:
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Evan Quan authored
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by:
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Evan Quan authored
And to fit more accurately what the cod does. Signed-off-by:
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Evan Quan authored
The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14. Signed-off-by:
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Evan Quan authored
And different workaround will be applied based on hybrid cdr bit. V2: add pmfw version guard to make sure the new workaround applied only with pmfw >= 42.53.0 Signed-off-by: -
Evan Quan authored
By uploading dummy pstate tables. Signed-off-by:
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Evan Quan authored
This dummy reading buffer will be used for the new Navi1x UMC CDR workaround. Signed-off-by:
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Evan Quan authored
Drop the unused message(SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE). And do not apply this workaround when the max uclk frequency is greater than 750Mhz. Signed-off-by:
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Evan Quan authored
That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Signed-off-by:
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Evan Quan authored
This is needed for Navi1X only. And it may help for display missing or hang issue seen on some high resolution monitors. V2: no UCLK DPM enablement for Navi10 A0 secure SKU Signed-off-by:
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Evan Quan authored
So that ASIC specific actions can be added. V2: better namings Signed-off-by:
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- 15 Sep, 2020 15 commits
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Michel Dänzer authored
Don't check drm_crtc_state::active for this either, per its documentation in include/drm/drm_crtc.h: * Hence drivers must not consult @active in their various * &drm_mode_config_funcs.atomic_check callback to reject an atomic * commit. atomic_remove_fb disables the CRTC as needed for disabling the primary plane. This prevents at least the following problems if the primary plane gets disabled (e.g. due to destroying the FB assigned to the primary plane, as happens e.g. with mutter in Wayland mode): * The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID (which enables the cursor plane). * If the cursor plane was enabled, changing the legacy DPMS property value from off to on returned EINVAL. v2: * Minor changes to code comment and commit log, per review feedback. GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108 GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165 GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344Suggested-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Alex Deucher authored
Copy paste typo. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
Due to hardware bugs, scatter/gather display on raven requires a 1:1 IOMMU mapping, however, SME (System Memory Encryption) requires an indirect IOMMU mapping because the encryption bit is beyond the DMA mask of the chip. As such, the two are incompatible. Acked-by:
Joerg Roedel <jroedel@suse.de> Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
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YueHaibing authored
Add trigger_hotplug debugfs entry. Fixes: 6f77b2ac ("drm/amd/display: Add connector HPD trigger debugfs entry") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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YueHaibing authored
If parse_write_buffer_into_params() fails, we should free wr_buf before return. Fixes: 6f77b2ac ("drm/amd/display: Add connector HPD trigger debugfs entry") Reviewed-by:
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Bernard Zhao authored
In fnction is_cr_done & is_ch_eq_done, when done = false happened once, no need to circle left ln_count. This change is to make the code run a bit fast. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1003:4-9: WARNING: Comparison to bool drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1083:5-11: WARNING: Comparison to bool Acked-by:
Zheng Bin <zhengbin13@huawei.com> Signed-off-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:619:15-49: WARNING: Comparison to bool drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:629:15-49: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c:1243:14-25: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/si.c:1342:5-10: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:562:5-11: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:619:5-11: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3563:5-31: WARNING: Comparison to bool Acked-by:
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Zheng Bin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2805:5-11: WARNING: Comparison to bool Acked-by:
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Sandeep Raghuraman authored
This patch adds support for reporting sclk values for Radeon GPUs, where supported. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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