Add new binding document for pinctrl on IPQ9574
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20230316072940.29137-4-quic_devipriy@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add pinctrl driver for TLMM block found in SM7150 SoC.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20230311212114.108870-3-danila@jiaxyga.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add device tree binding Documentation details for Qualcomm SM7150
TLMM device
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230311212114.108870-2-danila@jiaxyga.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The Ralink pinctrl driver is now under the name of MediaTek MIPS pin
controller. Move the maintainer information accordingly. Add dt-binding
schema files. Add linux-mediatek@lists.infradead.org as an associated
mailing list.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230317213011.13656-22-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The MT7628 and MT7688 SoCs contain different pin muxing information,
therefore, should be split. This can be done now that there are compatible
strings to distinguish them from other SoCs.

Split the schema out to mediatek,mt76x8-pinctrl.yaml.

Remove mediatek,mt76x8-pinctrl from mt7620.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-21-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The RT3352 and RT5350 SoCs each contain different pin muxing information,
therefore, should be split. This can be done now that there are compatible
strings to distinguish them from other SoCs.

Split the schema out to ralink,rt3352-pinctrl.yaml and
ralink,rt5350-pinctrl.yaml.

Remove ralink,rt3352-pinctrl and ralink,rt5350-pinctrl from rt305x.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-20-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Set second level patternProperties to '^.*mux.*$' and '^.*conf.*$' on
mediatek,mt7986-pinctrl.yaml to be on par with other schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-19-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Drop the quotes from the referred schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-18-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Fix the location of the pinmux header files mentioned on the schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-17-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Change the style of description properties to plain style where there's no
need to preserve the line endings, and vice versa.

Fix capitalisation and indentation.

Fit the schemas to 80 columns for each line.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-16-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek"
to address the naming inconsistency.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-15-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-14-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-13-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par
with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-12-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be
on par with the compatible string and other mediatek dt-binding schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-11-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Rename schemas of pin controllers for MediaTek MT7620 and MT7621 SoCs to be
on par with other pin controllers for MediaTek SoCs.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-10-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add the new compatible strings for mt7620, mt76x8, and rt305x to be able to
properly document the pin muxing information of each SoC, or SoCs that use
the same pinmux data.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-9-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Drop the quotes from the referred schemas.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-8-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Move additionalProperties to the top. It's easier to read than after a long
indented section.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-7-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The OF_GPIO option is enabled by default when GPIOLIB is enabled, and
cannot be disabled. Remove it as a reverse dependency where GPIOLIB is also
set as a reverse dependency.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230317213011.13656-6-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek
introduced new SoCs which utilise this platform. Move the driver to
mediatek pinctrl directory. Rename the ralink core driver to mtmips.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/r/20230317213011.13656-5-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Split the driver out to pinctrl-mt76x8.c. Remove including the unnecessary
headers since is_mt76x8() is not being used anymore.

Introduce a new compatible string to be able to document the pin muxing
information properly.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230317213011.13656-4-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add new compatible strings to make every SoC, or SoCs that use the same
pinmux data have a unique compatible string. This ensures that the pin
muxing information of every SoC, or a set of SoCs that use the same pinmux
data can be properly documented.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230317213011.13656-3-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

There have been stable releases with the ralink,rt2880-pinmux compatible
string included. Having it removed breaks the ABI. Reintroduce it.

Fixes: e5981cd4 ("pinctrl: ralink: add new compatible strings for each pinctrl subdriver")
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230317213011.13656-2-arinc.unal@arinc9.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

All LPASS pins have basic GPIO function and most of the code is ready
for that.  Add missing glue pieces to allow LPASS pins to work as GPIO,
which is going to be used on MTP8550 and QRD8550 boards.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230309154949.658380-4-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

When choosing GPIO function for pins, use the same glitch-free method as
main TLMM pinctrl-msm.c driver in msm_pinmux_set_mux().  This replicates
the commit d21f4b7f ("pinctrl: qcom: Avoid glitching lines when we
first mux to output") to LPASS pin controller with same justification.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230309154949.658380-3-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The set_mux callback in SoC TLMM driver (pinctrl-msm.c) uses "group",
not "group_num" for the number of the pin group.  Other places of
lpass-lpi also use "group", so let's be consistent for code readability.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230309154949.658380-2-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

As per Hardware Programming Guide, when configuring pin as output,
set the pin value before setting output-enable (OE).  Similar approach
is in main SoC TLMM pin controller.

Cc: <stable@vger.kernel.org>
Fixes: 6e261d10 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230309154949.658380-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add MPM <-> TLMM pin mappings to allow for waking up the AP from sleep
through MPM-connected pins.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230308213651.647098-1-konrad.dybcio@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The pioc_idx member of struct at91_gpio_chip is write only, just remove it.
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230216-gpio-at91-immutable-v2-2-326ef362dbc7@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

To help gpiolib not fiddle around with the internals of the irqchip
flag the chip as immutable, adding the calls into the gpiolib core
required to do so.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230216-gpio-at91-immutable-v2-1-326ef362dbc7@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The declaration of s32_pinctrl_suspend/s32_pinctrl_resume is hidden
in an #ifdef, causing a compilation failure when CONFIG_PM_SLEEP is
disabled:

drivers/pinctrl/nxp/pinctrl-s32g2.c:754:38: error: 's32_pinctrl_suspend' undeclared here (not in a function); did you mean 's32_pinctrl_probe'?
drivers/pinctrl/nxp/pinctrl-s32g2.c:754:9: note: in expansion of macro 'SET_LATE_SYSTEM_SLEEP_PM_OPS'
  754 |         SET_LATE_SYSTEM_SLEEP_PM_OPS(s32_pinctrl_suspend,
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~

Remove the bogus #ifdef and __maybe_unused annation on the global
functions, and instead use the proper LATE_SYSTEM_SLEEP_PM_OPS()
macro to pick set the function pointer.

As the function definition is still in the #ifdef block, this leads
to the correct code in all configurations.

Fixes: fd84aaa8 ("pinctrl: add NXP S32 SoC family support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230310140250.359147-1-arnd@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The driver will match mostly by DT table (even thought there is regular
ID table) so there is little benefit in of_match_ptr (this also allows
ACPI matching via PRP0001, even though it might not be relevant here).
This also fixes !CONFIG_OF error:

  drivers/pinctrl/pinctrl-sx150x.c:833:34: error: ‘sx150x_of_match’ defined but not used [-Werror=unused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230312132702.352832-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Link: https://lore.kernel.org/r/20230306144641.21955-1-quic_mdalam@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The description of second IO address is a bit confusing.  It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base.  The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

No instance of "struct imx_pinctrl_soc_info" sets '.generic_pinconf =
true', so all of this is effectively dead code.

To make it easier to understand the actual code, remove all the unused
cruft. This effectively reverts a5cadbbb ("pinctrl: imx: add
generic pin config core support").

It was only in use by a single SOC (imx7ulp) for a few releases, and
the commit message of dbffda08 ("pinctrl: fsl: imx7ulp: change to
use imx legacy binding") suggests that it won't be used in the
future. Certainly no new user has appeared in 20+ releases, and should
the need arise, this can be dug out of git history again.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Reviewed-by: Fabio Estevam  <festevam@gmail.com>
Link: https://lore.kernel.org/r/20230302072132.1051590-1-linux@rasmusvillemoes.dkSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use %u instead of %d as line is unsigned int.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230302110116.342486-5-claudiu.beznea@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use dev_err_probe() to simplify the code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230302110116.342486-4-claudiu.beznea@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use device_get_match_data() to simplify the code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230302110116.342486-3-claudiu.beznea@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use devm_clk_get_enabled() to simplify the code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230302110116.342486-2-claudiu.beznea@microchip.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>