Commits · 5c5ae7157d78e59e062dd35fbe9dec4de852bec2 · Kirill Smelkov / linux

05 Jul, 2013 19 commits
- drm/nvc0-/gr: remove some more of the hardcoded register writes · 5c5ae715
  Ben Skeggs authored Jul 05, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  5c5ae715
- drm/nvc0-/gr: factor out yet more unknown magic into versioned functions · d196e16e
  Ben Skeggs authored Jul 05, 2013
```
NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this.  We previously weren't doing these
register modifications, and NVIDIA do.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  d196e16e
- drm/nvd7/devinit: use fermi class, not tesla · 0bfd6f73
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  0bfd6f73
- drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16 · 60a4acd7
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  60a4acd7
- drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode · f8adeb82
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  f8adeb82
- drm/nvf0/gr: build cs ucode for GK110 · 8f6fe267
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  8f6fe267
- drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs · 960b4381
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  960b4381
- drm/nvf0/gr: fix ddx shaders locking up on me · 0085a605
  Ben Skeggs authored Jul 04, 2013
```
This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  0085a605
- drm/nvc0/devinit: minor typo · 18ac4246
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  18ac4246
- drm/nvf0/gr: enable support, if external cs ucode is available · 9d1c4c51
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  9d1c4c51
- drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding · b054aadf
  Ben Skeggs authored Jul 04, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  b054aadf
- drm/nvf0/ce: enable support · 9ec2dbba
  Ben Skeggs authored May 02, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  9ec2dbba
- drm/nvf0/fifo: enable support · 56fbd2b6
  Ben Skeggs authored May 02, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  56fbd2b6
- drm/nvd7/gr: initial support · 26410c67
  Maarten Lankhorst authored Jul 04, 2013
```
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  26410c67
- drm/nvc0-/gr: generate cs register lists from grctx data · a32b2ffb
  Ben Skeggs authored Jul 01, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  a32b2ffb
- drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs · 70f824ac
  Ben Skeggs authored Jul 01, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  70f824ac
- drm/nve0-/gr: some new gpc registers can have multiple copies · 5ee86c41
  Ben Skeggs authored Jul 01, 2013
```
GK110 exposes more than one, and needs to be dealt with in the ctxsw
ucode just like the TPC sets are.

Broadcast is at +0xe00.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  5ee86c41
- drm/nvc0-/gr: pull out a group of separately context-switched gpc regs · c03ff9e8
  Ben Skeggs authored Jul 01, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  c03ff9e8
- drm/nvc0-/gr: make register lists from initvals functions · 30f4e087
  Ben Skeggs authored Jun 09, 2013
```
Generated context verified to be the same for all supported chipsets.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  30f4e087
01 Jul, 2013 21 commits
- drm/nvd0-/disp: handle case where display engine is missing/disabled · 791dc143
  Maarten Lankhorst authored Jun 27, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  791dc143
- drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 · e99716f1
  Ben Skeggs authored Jun 05, 2013
```
No code changes, proven by envyas producing identical binaries.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  e99716f1
- drm/nouveau/bsp/nv84: initial vp2 engine implementation · 05f9a5bc
  Ilia Mirkin authored Jun 27, 2013
```
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  05f9a5bc
- drm/nouveau/vp/nv84: initial vp2 engine implementation · a0376b14
  Ilia Mirkin authored Jun 27, 2013
```
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  a0376b14
- drm/nouveau/core: xtensa engine base class implementation · 44b1e3bd
  Ilia Mirkin authored Jun 27, 2013
```
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  44b1e3bd
- drm/nouveau/vdec: fork vp3 implementations from vp2 · 0d4a1450
  Ilia Mirkin authored Jun 27, 2013
```
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  0d4a1450
- drm/nouveau/core: move falcon class to engine/ · a0fd4ec8
  Ben Skeggs authored Jun 27, 2013
```
Not really "core" per-se.  About to merge Ilia's work adding another
similar class for the VP2 xtensa engines, so, seems like a good time to
move all these to engine/.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  a0fd4ec8
- drm/nouveau/kms: don't fail if there's no dcb table entries · d2898713
  Ben Skeggs authored Jun 25, 2013
```
Fixes module not loading on Tesla K20.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  d2898713
- drm/nouveau: remove limit on gart · 79442c3a
  Maarten Lankhorst authored Jun 17, 2013
```
Most graphics cards nowadays have a multiple of this limit as their vram,
so limiting GART doesn't seem to make much sense.
Signed-off-by: Maarten &gt;Lnkhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  79442c3a
- drm/nouveau/vm: perform a bar flush when flushing vm · 36798b61
  Maarten Lankhorst authored Jun 11, 2013
```
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes
internally".

nvidia always seems to do this flush after writing values.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  36798b61
- drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches · 57f0ec15
  Ben Skeggs authored May 14, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  57f0ec15
- drm/nvc8/gr: update initial register/context values · eb12f57b
  Ben Skeggs authored May 14, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  eb12f57b
- drm/nvc4/gr: update initial register/context values · dba50728
  Ben Skeggs authored May 14, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  dba50728
- drm/nvc1/gr: update initial register/context values · 58ef2305
  Ben Skeggs authored May 13, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  58ef2305
- drm/nvc3/gr: update initial register/context values · 8b637ae3
  Ben Skeggs authored May 13, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  8b637ae3
- drm/nvc0/gr: update initial register/context values · d8b02dbb
  Ben Skeggs authored May 13, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  d8b02dbb
- drm/nvd9/gr: update initial register/context values · 37c3afd0
  Ben Skeggs authored May 13, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  37c3afd0
- drm/nve4/gr: update initial register/context values · 1dd44acf
  Ben Skeggs authored May 07, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  1dd44acf
- drm/nvc0-/gr: bump maximum gpc/tpc limits · a8004a9e
  Ben Skeggs authored May 06, 2013
```
Needed for GK110, separate commit to catch any unexpected breaks to
other parts of the code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  a8004a9e
- drm/nvf0/gr: initial register/context setup · cb1e06e0
  Ben Skeggs authored May 06, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  cb1e06e0
- drm/nve7/gr: update initial register/context values · 507cd5b5
  Ben Skeggs authored May 06, 2013
```
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
```
  507cd5b5