- 01 Jun, 2020 4 commits
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Stephen Boyd authored
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for Qualcomm's MSM8939 Generic Clock Controller - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips * clk-mmp: clk: mmp2: Add audio clock controller driver dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding clk: mmp2: Add support for power islands dt-bindings: marvell,mmp2: Add ids for the power domains dt-bindings: clock: Make marvell,mmp2-clock a power controller clk: mmp2: Add the audio clock clk: mmp2: Add the I2S clocks clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() clk: mmp2: Move thermal register defines up a bit dt-bindings: marvell,mmp2: Add clock id for the Audio clock dt-bindings: marvell,mmp2: Add clock id for the I2S clocks clk: mmp: frac: Allow setting bits other than the numerator/denominator clk: mmp: frac: Do not lose last 4 digits of precision * clk-intel: clk: intel: remove redundant initialization of variable rate64 clk: intel: Add CGU clock driver for a new SoC dt-bindings: clk: intel: Add bindings document & header file for CGU * clk-ingenic: clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused clk: X1000: Add FIXDIV for SSI clock of X1000. dt-bindings: clock: Add and reorder ABI for X1000. clk: Ingenic: Add CGU driver for X1830. dt-bindings: clock: Add X1830 clock bindings. clk: Ingenic: Adjust cgu code to make it compatible with X1830. clk: Ingenic: Remove unnecessary spinlock when reading registers. * clk-qcom: clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src dt-bindings: clock: Add YAML schemas for QCOM A53 PLL clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller clk: qcom: gcc: Add support for Secure control source clock dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID clk: qcom: gcc: Add support for a new frequency for SC7180 clk: qcom: Add DT bindings for MSM8939 GCC clk: qcom: gcc: Add missing UFS clocks for SM8150 clk: qcom: gcc: Add GPU and NPU clocks for SM8150 clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc clk: qcom: gdsc: Handle GDSC regulator supplies clk: qcom: msm8916: Fix the address location of pll->config_reg * clk-silabs: clk: clk-si5341: Add support for the Si5345 series
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Stephen Boyd authored
* clk-unisoc: clk: sprd: add mipi_csi_xx gate clocks clk: sprd: add dt-bindings include for mipi_csi_xx clocks dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A clk: sprd: check its parent status before reading gate clock clk: sprd: return correct type of value for _sprd_pll_recalc_rate clk: sprd: mark the local clock symbols static * clk-trivial: clk: versatile: remove redundant assignment to pointer clk clk: clk-xgene: Fix a typo in Kconfig clk: Remove unused inline function clk_debug_reparent * clk-bcm: clk: bcm2835: Constify struct debugfs_reg32 clk: bcm2835: Remove casting to bcm2835_clk_register clk: bcm2835: Fix return type of bcm2835_register_gate * clk-st: clk: clk-flexgen: fix clock-critical handling * clk-ast2600: clk: ast2600: Fix AHB clock divider for A1
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Stephen Boyd authored
Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-next - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - Support for Intel Agilex clks * clk-tegra: clk: tegra: Add Tegra210 CSI TPG clock gate clk: tegra30: Use custom CCLK implementation clk: tegra20: Use custom CCLK implementation clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: Add custom CCLK implementation clk: tegra: Remove the old emc_mux clock for Tegra210 clk: tegra: Implement Tegra210 EMC clock clk: tegra: Export functions for EMC clock scaling clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Rename Tegra124 EMC clock source file dt-bindings: clock: tegra: Add clock ID for CSI TPG clock * clk-imx: clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx: add imx8m_clk_hw_composite_bus clk: imx: add mux ops for i.MX8M composite clk clk: imx8m: migrate A53 clk root to use composite core clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx: imx8mp: fix pll mux bit clk: imx8m: drop clk_hw_set_parent for A53 dt-bindings: clocks: imx8mp: Add ids for audiomix clocks clk: imx: Add helpers for passing the device as argument clk: imx: pll14xx: Add the device as argument when registering clk: imx: gate2: Allow single bit gating clock clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait clk: imx: clk-sscg-pll: Remove unnecessary blank lines clk: imx: drop the dependency on ARM64 for i.MX8M clk: imx7ulp: make it easy to change ARM core clk clk: imx: imx6ul: change flexcan clock to support CiA bitrates * clk-zynq: clk: zynqmp: Make zynqmp_clk_get_max_divisor static clk: zynqmp: Update fraction clock check from custom type flags clk: zynqmp: Add support for custom type flags clk: zynqmp: fix memory leak in zynqmp_register_clocks clk: zynqmp: Fix invalid clock name queries clk: zynqmp: Fix divider2 calculation clk: zynqmp: Limit bestdiv with maxdiv * clk-socfpga: clk: socfpga: agilex: add clock driver for the Agilex platform dt-bindings: documentation: add clock bindings information for Agilex clk: socfpga: add const to _ops data structures clk: socfpga: remove clk_ops enable/disable methods clk: socfpga: stratix10: use new parent data scheme * clk-at91: clk: at91: allow setting all PMC clock parents via DT clk: at91: allow setting PCKx parent via DT clk: at91: optimize pmc data allocation clk: at91: pmc: decrement node's refcount clk: at91: pmc: do not continue if compatible not located clk: at91: Add peripheral clock for PTC * clk-ti: clk: ti: dra7: remove two unused symbols clk: ti: dra7xx: fix RNG clock parent clk: ti: dra7xx: mark MCAN clock as DRA76x only clk: ti: dra7xx: fix gpu clkctrl parent clk: ti: omap5: Add proper parent clocks for l4-secure clocks clk: ti: omap4: Add proper parent clocks for l4-secure clocks clk: ti: composite: fix memory leak
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Stephen Boyd authored
Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next - Allow the COMMON_CLK config to be selectable * clk-selectable: clk: Move HAVE_CLK config out of architecture layer MIPS: Loongson64: Drop asm/clock.h include ARM: mmp: Remove legacy clk code clk: Allow the common clk framework to be selectable mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF MIPS: Remove redundant CLKDEV_LOOKUP selects h8300: Remove redundant CLKDEV_LOOKUP selects arm64: tegra: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant CLKDEV_LOOKUP selects ARM: Remove redundant COMMON_CLK selects * clk-amlogic: clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: export the HDMI system clock * clk-renesas: dt-bindings: clock: renesas: mstp: Convert to json-schema dt-bindings: clock: renesas: div6: Convert to json-schema clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects clk: renesas: cpg-mssr: Add R8A7742 support dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros MAINTAINERS: Add DT Bindings for Renesas Clock Generators clk: renesas: r9a06g032: Fix some typo in comments dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support * clk-samsung: clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough; clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical * clk-allwinner: clk: sunxi: Fix incorrect usage of round_down()
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- 29 May, 2020 1 commit
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Mike Looijmans authored
Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent to the Si5341 family, but with more clock input options (which are not supported yet by this driver). Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> Link: https://lkml.kernel.org/r/20200507061544.11388-1-mike.looijmans@topic.nlAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 28 May, 2020 22 commits
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Jeffrey Hugo authored
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power savings. Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by:
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.comSigned-off-by:
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Stephen Boyd authored
This device id table is passed to of_match_node() later on in probe, but on CONFIG_OF=n builds of_match_node() doesn't do anything with the arguments. Lets just mark the table unused so that the compiler doesn't complain about this. drivers/clk/ingenic/tcu.c:326:34: warning: unused variable 'ingenic_tcu_of_match' [-Wunused-const-variable] static const struct of_device_id ingenic_tcu_of_match[] __initconst = { ^ 1 warning generated. Reported-by:kbuild test robot <lkp@intel.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, and ensure that it initialized before "X1000_CLK_SSIMUX" when initializing the clocks. 2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU, and gates of CPU, PCLK are also added. 3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-8-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, it must between "X1000_CLK_SSIPLL" and "X1000_CLK_SSIMUX", otherwise an error will occurs when initializing the clock. These ABIs are only used for X1000, and I'm sure that no other devicetree out there is using these ABIs, so we should be able to reorder them. 2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add support for the clocks provided by the CGU in the Ingenic X1830 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add the clock bindings for the X1830 Soc from Ingenic. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
It is not necessary to use spinlock when reading registers, so remove it from cgu.c. Suggested-by:
Paul Burton <paulburton@kernel.org> Signed-off-by:
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Colin Ian King authored
The variable rate64 is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lkml.kernel.org/r/20200528221219.535804-1-colin.king@canonical.comSigned-off-by:
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Lubomir Rintel authored
This is a driver for a block that generates master and bit clocks for the I2S interface. It's separate from the PMUs that generate clocks for the peripherals. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-14-lkundrak@v3.skSigned-off-by:
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Lubomir Rintel authored
This describes the bindings for a controller that generates master and bit clocks for the I2S interface. Signed-off-by:
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Lubomir Rintel authored
Apart from the clocks and resets, the PMU hardware also controls power to peripherals that are on separate power islands. On MMP2, that's the GC860 GPU and the SSPA audio interface, while on MMP3 also the camera interface is on a separate island, along with the pair of GC2000 and GC300 GPUs and the SSPA. Signed-off-by:
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Lubomir Rintel authored
On MMP2 the audio and GPU blocks are on separate power islands. On MMP3 the camera block's power is also controlled separately. Add the numbers that we could use to refer to the power domains for respective power islands from the device tree. Signed-off-by:
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Lubomir Rintel authored
This is a binding for the MMP2 power management units. As such apart from providing the clocks, they also manage the power islands. Signed-off-by:
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Lubomir Rintel authored
This clocks the Audio block. Signed-off-by:
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Lubomir Rintel authored
A pair of fractional clock sources for PLLs and gates. Signed-off-by:
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Lubomir Rintel authored
This is a trivial rename for a routine that registers more clock sources than the PLLs -- there's also a XO. Signed-off-by:
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Lubomir Rintel authored
A trivial change to keep the sorting sane. The APBC registers are happier when they are grouped together, instead of mixed with the APMU ones. Signed-off-by:
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Lubomir Rintel authored
This clocks the Audio block. Signed-off-by:
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Lubomir Rintel authored
There are two of these on a MMP2. Signed-off-by:
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Lubomir Rintel authored
For the I2S fractional clocks, there are more bits that need to be set for the clock to run. Their actual meaning is unknown. Signed-off-by:
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Lubomir Rintel authored
While calculating the output rate of a fractional divider clock, the value is divided and multipled by 10000, discarding the least significant digits -- presumably to fit the intermediate value within 32 bits. The precision we're losing is, however, not insignificant for things like I2S clock. Maybe also elsewhere, now that since commit ea56ad60 ("clk: mmp2: Stop pretending PLL outputs are constant") the parent rates are more precise and no longer rounded to 10000s. Signed-off-by:
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- 27 May, 2020 13 commits
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Eddie James authored
The latest specs for the AST2600 A1 chip include some different bit definitions for calculating the AHB clock divider. Implement these in order to get the correct AHB clock value in Linux. Signed-off-by:
Eddie James <eajames@linux.ibm.com> Link: https://lkml.kernel.org/r/20200408203616.4031-1-eajames@linux.ibm.com Fixes: d3d04f6c ("clk: Add support for AST2600 SoC") Signed-off-by:
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Alain Volmat authored
Fixes an issue leading to having all clocks following a critical clocks marked as well as criticals. Fixes: fa6415af ("clk: st: clk-flexgen: Detect critical clocks") Signed-off-by:
Alain Volmat <avolmat@me.com> Link: https://lkml.kernel.org/r/20200322140740.3970-1-avolmat@me.comReviewed-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Rikard Falkeborn authored
bcm2835_debugfs_clock_reg32 is never changed and can therefore be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 26598 16088 64 42750 a6fe drivers/clk/bcm/clk-bcm2835.o After: text data bss dec hex filename 26662 16024 64 42750 a6fe drivers/clk/bcm/clk-bcm2835.o Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lkml.kernel.org/r/20200508220238.4883-1-rikard.falkeborn@gmail.comSigned-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200527053638.31439-5-zhang.lyra@gmail.comSigned-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
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Chunyan Zhang authored
mipi_csi_xx clocks are used by camera sensors. Signed-off-by:
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Chunyan Zhang authored
Some clocks only can be accessed if their parent is enabled. mipi_csi_xx clocks on SC9863A are an examples. We have to ensure the parent clock is enabled when reading those clocks. Signed-off-by:
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Colin Ian King authored
The pointer clk is being initialized with a value that is never read and is being updated with a new value later on. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Jason Yan authored
Fix the following gcc warning: drivers/clk/ti/clk-7xx.c:320:43: warning: ‘dra7_gpu_sys_clk_data’ defined but not used [-Wunused-const-variable=] static const struct omap_clkctrl_div_data dra7_gpu_sys_clk_data __initconst = { ^~~~~~~~~~~~~~~~~~~~~ drivers/clk/ti/clk-7xx.c:315:27: warning: ‘dra7_gpu_sys_clk_parents’ defined but not used [-Wunused-const-variable=] static const char * const dra7_gpu_sys_clk_parents[] __initconst = { ^~~~~~~~~~~~~~~~~~~~~~~~ Reported-by:Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Link: https://lkml.kernel.org/r/20200417073523.42520-1-yanaijie@huawei.comAcked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Michał Mirosław authored
We need to have clocks accessible via phandle to select them as peripheral clock parent using assigned-clock-parents in DT. Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.plSigned-off-by:
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Michał Mirosław authored
This exposes PROGx clocks for use in assigned-clocks DeviceTree property for selecting PCKx parent clock. Signed-off-by:
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Michał Mirosław authored
Alloc whole data structure in one block. This makes the code shorter, more efficient and easier to extend in following patch. Signed-off-by:
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Claudiu Beznea authored
of_find_matching_node() increment node's refcount. Call of_node_put() to decrement it after it was used. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lkml.kernel.org/r/1588508289-10140-2-git-send-email-claudiu.beznea@microchip.comSigned-off-by:
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