- 24 Apr, 2023 27 commits
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Josip Pavic authored
[Why & How] Provide option for vendors to specify a custom brightness-to-backlight conversion profile. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo Chen authored
[Why & How] Per HW team request, we're lowering the minimum Z8 residency time to 2000us. This enables Z8 support for additional modes we were previously blocking like 2k>60hz Cc: stable@vger.kernel.org Tested-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Alvin Lee authored
Enable SubVP on PSR panels now that we have FW support Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
This feature is meant to unblock PSTATE for certain high end display configs on dcn315. This is achieved by allocating CRB to detile buffer based on display requirements to meet pstate latency hiding needs. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Alvin Lee authored
- Due to hardware related QoS issues, we need to limit certain SKUs with less memory channels to DPM1 and above. - At DPM0 + workload running, the urgent return latency can exceed 15us (the expected maximum is 4us) which results in underflow Cc: stable@vger.kernel.org Tested-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Acked-by:
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JinZe.Xu authored
[Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by:
JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by:
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Alvin Lee authored
Reorder FW feature caps struct variable order to ensure backwards compatability is maintained for older FW Tested-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Alex Hung authored
[Why] When userspace (IGT) inserts EDID with audio data (ELD), EDID is not updated. [How] Implements force function (amdgpu_dm_connector_funcs_force) in amdgpu_dm_connector_funcs to create emulated sink and to handle EDID. Tested-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Wenchieh Chien <wenchieh.chien@amd.com> Signed-off-by:
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Aric Cyr authored
Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Add feature caps for Subvp + PSR so driver is back compatible Tested-by:
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Alex Deucher authored
Provide a debugfs interface to access the MQD. Useful for debugging issues with the CP and MES hardware scheduler. v2: fix missing unreserve/unmap when pos >= size (Alex) Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
It varies by generation and we need to know the size to expose this via debugfs. Reviewed-by:
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Alex Deucher authored
So UMDs can determine whether the kernel supports this. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986Signed-off-by:
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Xiaogang Chen authored
amdgpu_ttm_tt_get_user_pages can fail(-EFAULT). If it failed mem has no associated hmm range or user_pages associated. Keep it at process_info->userptr_inval_list and mark mem->invalid until following scheduled attempts can valid it. Signed-off-by:
Xiaogang Chen <Xiaogang.Chen@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] 32ms delay was added to resolve issue with a specific sink, however this same delay also introduces erroneous link training failures with certain sink devices. [HOW] Only apply the 32ms delay for offending devices instead of globally. Tested-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Hersen Wu authored
[Why] implementation change of drm_edid_override_set since linux kernel 6.1, edid from debugfs is saved into connector->edid_override immediatey, not saved to connector->edid_blob_ptr at the same time. [How] call new drm_edid function drm_connector_update_edid_property to assign connector->edid_blob_ptr with override edid from debugfs. Tested-by:
Chao-kai Wang <Stylon.Wang@amd.com> Acked-by:
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Alex Deucher authored
Use the new callback to fetch the data. Return an error if not supported. UMDs should use this query to check whether shadow buffers are supported and if so what size they should be. v2: return an error rather than a zerod structure. v3: drop GDS, move into dev_info structure. Data will be 0 if not supported. v4: drop local variable r Signed-off-by: -
Alex Deucher authored
Used to get the size and alignment requirements for the gfx shadow buffer for preemption. v2: use FW version check to determine whether to return a valid size here return an error if not supported (Alex) v3: drop GDS (Alex) v4: make amdgpu_gfx_shadow_info mandatory (Alex) Signed-off-by: -
Alex Deucher authored
To provide IP specific shadow sizes. UMDs will use this to query the kernel driver for the size of the shadow buffers. v2: make callback return an int (Alex) v3: drop GDS (Alex) Reviewed-by:
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Alex Deucher authored
Add UAPI to query the GFX shadow buffer requirements for preemption on GFX11. UMDs need to specify the shadow areas for preemption. v2: move into existing asic info query drop GDS as its use is determined by the UMD (Marek) v3: Update comments to note that alignment is base virtual alignment (Alex) Reviewed-by:Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Alex Deucher authored
We need to reset the shadow state every time we submit an IB and there needs to be a COND_EXEC packet after the SET_Q_PREEMPTION_MODE packet for it to work properly, so we should emit both of these packets regardless of whether there is a job present or not. Reviewed-by:
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Christian König authored
Add ring callback for gfx to update the CP firmware with the new shadow information before we process the IB. v2: add implementation for new packet (Alex) v3: add current FW version checks (Alex) v4: only initialize shadow on first use Only set IB_VMID when a valid shadow buffer is present (Alex) v5: Pass parameters rather than job to new ring callback (Alex) Reviewed-by: -
Christian König authored
Add support for submitting the shadow update packet when submitting an IB. Needed for MCBP on GFX11. v2: update API for CSA (Alex) v3: fix ordering; SET_Q_PREEMPTION_MODE most come before COND_EXEC Add missing check for AMDGPU_CHUNK_ID_CP_GFX_SHADOW in amdgpu_cs_pass1() Only initialize shadow on first use (Alex) v4: Pass parameters rather than job to new ring callback (Alex) v5: squash in change to call SET_Q_PREEMPTION_MODE/COND_EXEC before RELEASE_MEM to complete the UMDs use of the shadow (Alex) Reviewed-by: -
Alex Deucher authored
For GFX11, the UMD needs to allocate some shadow buffers to be used for preemption. The UMD allocates the buffers and passes the GPU virtual address to the kernel since the kernel will program the packet that specified these addresses as part of its IB submission frame. v2: UMD passes shadow init to tell kernel when to initialize the shadow Reviewed-by: -
Alex Deucher authored
Only set the supported flag if we have new enough CP FW. v2: update to the final firmware versions Acked-by:
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Jack Xiao authored
The fences associated with mes queue have to be freed up during amdgpu_ring_fini. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Use this to determine if we support the new SET_Q_PREEMPTION_MODE packet. Signed-off-by:
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- 21 Apr, 2023 13 commits
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Hamza Mahfooz authored
Currently, on a handful of ASICs. We allow the framebuffer for a given plane to exist in either VRAM or GTT. However, if the plane's new framebuffer is in a different memory domain than it's previous framebuffer, flipping between them can cause the screen to flicker. So, to fix this, don't perform an immediate flip in the aforementioned case. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354Reviewed-by:
Roman Li <Roman.Li@amd.com> Fixes: 81d0bcf9 ("drm/amdgpu: make display pinning more flexible (v2)") Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Arnd Bergmann authored
The dmub_abm_set_ambient_level() function has no caller and can just be removed, the other ones have a declaration in the header file and just need to see the prototype: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:122:14: error: no previous prototype for function 'dmub_abm_get_current_backlight' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:133:14: error: no previous prototype for function 'dmub_abm_get_target_backlight' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:144:6: error: no previous prototype for function 'dmub_abm_set_level' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:163:6: error: no previous prototype for function 'dmub_abm_set_ambient_level' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:183:6: error: no previous prototype for function 'dmub_abm_init_config' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:213:6: error: no previous prototype for function 'dmub_abm_set_pause' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:231:6: error: no previous prototype for function 'dmub_abm_set_pipe' [-Werror,-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.c:251:6: error: no previous prototype for function 'dmub_abm_set_backlight_level' [-Werror,-Wmissing-prototypes] Fixes: b8fe5637 ("drm/amd/display: Refactor ABM feature") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Aric Cyr authored
This DC version brings along: - FW Release 0.0.162.0 - Enable FPO+Vactivate - Support for VESA SCR - Refactor DMUB commands - Fixes in secure display, modeset, memleak and more - Picked up missed patches in history Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Add Enum and documenation related to FAMS (Firmware Assisted Memclk Switching) and CAB (Cache As Buffer) Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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hackyzh002 authored
The type of size is unsigned int, if size is 0x40000000, there will be an integer overflow, size will be zero after size *= sizeof(uint32_t), will cause uninitialized memory to be referenced later. Reviewed-by:
hackyzh002 <hackyzh002@gmail.com> Signed-off-by:
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hackyzh002 authored
The type of size is unsigned, if size is 0x40000000, there will be an integer overflow, size will be zero after size *= sizeof(uint32_t), will cause uninitialized memory to be referenced later Reviewed-by:
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Aurabindo Pillai authored
DCN31 supports FAMS, but this was not correctly set to the hardware setup sequence. This commit fixes this issue by setting the MCLK switch capability based on the feature capability retrieved from the DMUB. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] The bit for flip addr is being set causing the determination for FAST vs MEDIUM to always return MEDIUM when plane info is provided as a surface update. This causes extreme stuttering for the typical atomic update path on Linux. [How] Don't use update_flags->raw for determining FAST vs MEDIUM. It's too fragile to changes like this. Explicitly specify the update type per update flag instead. It's not as clever as checking the bits itself but at least it's correct. Fixes: aa5fdb1a ("drm/amd/display: Explicitly specify update type per plane info change") Reviewed-by:
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Zhongwei authored
[Why] disable_vbios_mode_if_required() will set dpms_off to false during boot when pixel clk dismatches with driver requires. This will cause extra backlight on and off if OS call 2 times setmode. [How] Set dpms_off to true to keep power_off and let OS control backlight by display's powerState. Reviewed-by:
Zhongwei <Zhongwei.Zhang@amd.com> Tested-by:
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Po-Ting Chen authored
Base on PSRSU specification, every seletive update frame need to use two SDP to indicate the frame active range. So we occupy another GSP1 for PSRSU execution. Reviewed-by:
Po-Ting Chen <robin.chen@amd.com> Tested-by:
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Igor Kravchenko authored
Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Reviewed-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Krunoslav Kovac authored
Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps for each ASIC. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by:
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