- 24 Oct, 2014 14 commits
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Gustavo Padovan authored
Now that universal planes are in place we don't need this plane unref on failures. Suggested-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Gustavo Padovan authored
Fold intel_pipe_set_base() in the update primary plane path merging pieces of code that are common to both paths. Basically the the pin/unpin procedures are the same for both paths and some checks can also be shared (some of the were moved to the check() stage) v2: take Ville's comments: - remove unnecessary plane check - move mutex lock to inside the conditional - make the pin fail message a debug one - add a fixme for the fastboot hack - call intel_frontbuffer_flip() after FBC update v3: take more Ville's comments: - fold update code under if (intel_crtc->active), and do the visible/!visible split inside. - check ret inside the same conditional we assign it v4: don't use intel_enable_primary_hw_plane(), the primary_enabled check inside will break page flips v5: take more Ville's comments: - set primary_enabled to true and add BDW hack - unify if (old_fb) and if (old_fb != fb) v6: take more Ville's comments: - make was_primary bool and fix its check - add the BDW vblank wait comment Suggested-by:
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Damien Lespiau authored
As stated in the few previous commits, IS_ULT/ULX() is better per-platform as it has different consequences depending on the platform. We now can get rid of it. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Damien Lespiau authored
IS_ULT() wasn't taking into account SKL so we had a warn with SPT-LP. We don't realy need those checks here, and as we don't need to introduce IS_SKL_ULT/ULX() at the moment, let's just drop them. Signed-off-by:
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Damien Lespiau authored
hsw_get_cdclk_freq() is really just HSW, so we can use IS_HSW_ULT() instead of IS_ULT() there. Signed-off-by:
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Damien Lespiau authored
The quality of being a ULT or ULX package doesn't tell anything across generations and so a global IS_ULT() macro doesn't make much sense, esp. as we're adding new products. So, spell out which ULT/ULX SKUs we are talking about here, namely HSW and BDW. Signed-off-by:
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Damien Lespiau authored
HAS_IPS() has a '|| IS_BROADWELL()', no need to check for IS_BDW_ULT(). Signed-off-by:
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Damien Lespiau authored
No need to add the BDW pci ULT/ULX checks inside a if (IS_HASWELL(dev)) code path. Signed-off-by:
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Daniel Vetter authored
v2: Fix spelling fail. Reviewed-by:
Daniel Vetter <daniel.vetter@intel.com>
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Daniel Vetter authored
This simplifies the code in the vlv irq handler. Also this now means that we correctly filter underruns on gen2-4. And as the real upshot I need to document one less function for the fifo underrun code. v2: Shorten one long line. Reviewed-by:
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Daniel Vetter authored
Way too much copypasta all over. And this also clarifies a bit what's going on since it separates the "do we have an underrun irq" from the "should we report the underrun" check. v2: Fix excessively long lines. Reviewed-by:
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Daniel Vetter authored
It's the new rule! Reviewed-by:
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Daniel Vetter authored
Prep work for some nice documentation. Requires that we export the display irq enable/disable functions on ilk/ibx. But we already export them for vlv/i915. So not more inconsistency. v2: Rebase on top of skl stage 1. Reviewed-by:
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Daniel Vetter authored
This reverts commit 8c50f10d. It's not yet solid and Dave objected to pulling the tree in its current state. Cc: Michel Thierry <michel.thierry@intel.com> Cc: Dave Airlie <airlied@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> References: http://mid.mail-archive.com/CAPM=9ty2r1MLE=wzC-_vNSUzXVqAyXiGgocpSV9qOp0gzpK3xA@mail.gmail.com References: http://lists.freedesktop.org/archives/intel-gfx/2014-October/053926.htmlAcked-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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- 21 Oct, 2014 1 commit
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Daniel Vetter authored
So I've sent the first pull request to Dave and I expect his request for a merge tree any second now ;-) More seriously I have some pending patches for 3.19 that depend upon both trees, hence backmerge. Conflicts are all trivial. Conflicts: drivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/intel_display.c v2: Of course I've forgotten the fixup script for the silent conflict. Signed-off-by:
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- 16 Oct, 2014 2 commits
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Jani Nikula authored
Fix short vs. long hpd detection for non-g4x and non-pch split platforms. Broken since introduction in commit 13cf5504 Author: Dave Airlie <airlied@redhat.com> Date: Wed Jun 18 11:29:35 2014 +1000 drm/i915: rework digital port IRQ handling (v2) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83175Reviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
On CHV the display DDC pins may be muxed to an alternate function if there's no need for DDC on a specific port, which is the case for eDP ports since there's no way to plug in a DP++ HDMI dongle. This causes problems when trying to determine if the port is present since the the DP_DETECTED bit is the latched state of the DDC SDA pin at boot. If the DDC pins are muxed to an alternate function the bit may indicate that the port isn't present. To work around this look at the VBT as well as the DP_DETECTED bit to determine if we should attempt registering an eDP port. Do this only for ports B and C since port D doesn't support eDP (no PPS/BLC). In theory someone could also wire up a normal DP port w/o DDC lines. That would just mean that simple DP++ HDMI dongles wouldn't work on such a port. With this change we would still fail to register such DP ports. But let's hope no one wires their board in such a way, and if they do we can extend the VBT checks to cover normal DP ports as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84265Signed-off-by:
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- 08 Oct, 2014 1 commit
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Paulo Zanoni authored
We were missing the pipe B/C vblank bits! Take a look at gen8_de_irq_postinstall for a comparison. This should fix a bunch of IGT tests. There are a few more things we could improve on this code, but this should be the minimal fix to unblock us. v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville) Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640 Testcase: igt/* Cc: stable@vger.kernel.org Signed-off-by:
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- 06 Oct, 2014 2 commits
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U. Artie Eoff authored
Move the duplicated DIV_ROUND_CLOSEST_ULL macro into the intel_drv.h header file so that it can be shared between intel_display.c and intel_panel.c. Signed-off-by:
U. Artie Eoff <ullysses.a.eoff@intel.com> Reviewed-By:
Joe Konno <joe.konno@intel.com> Signed-off-by:
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U. Artie Eoff authored
Improper truncated integer division in the scale() function causes actual_brightness != brightness. This (partial) work-around should be sufficient for a majority of use-cases, but it is by no means a complete solution. TODO: Determine how best to scale "user" values to "hw" values, and vice-versa, when the ranges are of different sizes. That would be a buggy scenario even with this work-around. The issue was introduced in the following (v3.17-rc1) commit: 6dda730e drm/i915: respect the VBT minimum backlight brightness Note that for easier backporting this commit adds a duplicated macro. A follow-up cleanup patch rectifies this for 3.18+ v2: (thanks to Chris Wilson) clarify commit message, use rounded division macro v3: -DIV_ROUND_CLOSEST() fails to build with CONFIG_X86_32=y. (Jani) -Use DIV_ROUND_CLOSEST_ULL() instead. (Damien) -v1 and v2 originally authored by Joe Konno. Signed-off-by:
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- 03 Oct, 2014 7 commits
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Daniel Vetter authored
Signed-off-by: -
Chris Wilson authored
We can use the same logic to walk the different bound/unbound lists during shrinker (as the unbound list is a degenerate case of the bound list), slightly compacting the code. Signed-off-by:
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Daniel Vetter authored
Just start with the basics for now. Since there's a lot of different functionality in i915_irq.c I've decided to split it into different sections and pull in just the relevant functions. Splitting into different files looks like a lot more work since the interrupt handlers do an awful lot of reuse all over. v2: Rebase onto changed function names. Signed-off-by:
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Daniel Vetter authored
It's the new world order! Not going full monty on these here and rolling this out throughout the subsequent call chains since this is just for the kerneldoc. Later on we can go more crazy, especially once we've embedded drm_device correctly. v2: Also frob the runtime_pm functions ... Signed-off-by:
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Daniel Vetter authored
Double negations just parse harder. Also this allows us to ditch some init code since clearing to 0 dtrt. Also ditch the assignment in intel_pm_setup, that's not redundant since we do the assignement now while setting up interrupts. While at it do engage in a bit of OCD and wrap up the few lines of setup/teardown code into little helper functions: intel_irq_fini for cleanup and intel_irq_init_hw for hw setup. v2: Use _install/_uninstall for the new wrapper function names as Paulo suggested. Signed-off-by:
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Ville Syrjälä authored
Clear the override bits to make sure the hardware manages the TX FIFO reset master on its own. v2: Squash with the earlier attempt at forcing the override bits Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Ville Syrjälä authored
The register can house two different swing marging/deemph settings at once. However only one gets used based on some other bits. Make sure we set those bits correctly to make the hardware use the settings we provided. Signed-off-by:
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- 02 Oct, 2014 3 commits
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Rodrigo Vivi authored
Even though it's unliky, we should check each aux transaction not just the first one. Also commit ce31d9f4 Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Mon Sep 29 18:29:52 2014 -0400 drm/i915: preserve other DP_TEST_SINK bits. added a new aux transaction before the one which was checked. Fix this. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Todd Previte <tprevite@gmail.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Daniel Vetter authored
Inspired by Ville constifying the send buffer for pach_aux. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: -
Ville Syrjälä authored
Use pack_aux() to construct the PSR exit DPMS D0 AUX message, and use the defines from dp_dp_helper.h to populate the message contents. v2: Use sizeof() for message size (Jani) Use a generic loop to write EDP_PSR_AUX_DATA registers Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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- 01 Oct, 2014 10 commits
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Daniel Vetter authored
This seems to have been accidentally lost in commit be62acb4 Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Fri Aug 30 16:19:28 2013 +0300 drm/i915: ban badly behaving contexts Without this real gpu hangs only log output at info level, which gets filtered away by piglit's testrunner. v2: Tune down to notice level. Note that we need to add drm/i915 so that at least the automatic igt dmesg filtering still picks it up. v3: git add and lack of coffee don't mix well. v4: Message is in between hw and sw reset, so switch verb to continuous form. v5: Use i915_stop_rings_allow_warn for consistency. For Chris' case of injecting lots of hangs I guess we need to revamp this all anyway when merging. For now this should plug the regression for piglit testing mesa. v6: Make it compile (Mika). Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kenneth Graunke <kenneth@whitecape.org> Reported-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
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Daniel Vetter authored
I've decided not to document the functions exported to the audio driver since really, they shouldn't exist ... v2: Improvements from Imre's review plus a few more spelling fixes I've spotted. Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Daniel Vetter authored
Allows us to mark it static and so forgoe the kerneldoc for it. Note that intel_power_domains_fini is also called from failure paths in the driver load sequence. But the call to runtime_pm_disable for that is harmless since by default runtime pm is already disabled. v2: Augment the commit message as discussed with Imre on irc. Reviewed-by:
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Daniel Vetter authored
I've decided to not move intel_display_port_power_domain because that's just a hack in our design ... Reviewed-by:
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Daniel Vetter authored
- fini goes with init, so call it intel_power_domains_fini. While at it shovel some of the fini code that leaked out of it back in. - give power_enabled functions the verb _is_ to make the meaning clearer. Also use a __ prefix instead of _unlocked to really discourage users. - rename runtime_pm_init/fini to enable/disable since that's what they do. Reviewed-by:
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Daniel Vetter authored
Geez is the audio hack ugly. Signed-off-by:
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Daniel Vetter authored
Another layer of indirection for just an lpt-only w/a is a bit excessive. Reduce it. This was added in commit 7d708ee4 Author: Imre Deak <imre.deak@intel.com> Date: Wed Apr 17 14:04:50 2013 +0300 drm/i915: HSW: allow PCH clock gating for suspend Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Daniel Vetter authored
Oh well. v2: Fix one more spelling fail Paulo spotted. Reviewed-by:
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Daniel Vetter authored
So I think I've spotted a small gap in the frontbuffer tracking while discussing the logic with Paulo on irc: 1. Userspace schedules gpu rendering to the current frontbuffer. This gets tracked in dev_priv->fb_tracking.busy_bits. 2. We pageflip a fully rendered buffer before the frontbuffer rendering completes. 3. The request retiring will never clear busy_bits (since at retire time the old frontbuffer won't have obj->frontbuffer_bits set), so these bits now are stuck until someone again does a bit of frontbuffer tracking. If we clear stale busy_bits in flip_prepare this gap is closed. Reviewed-by:
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Clint Taylor authored
Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing to the DPLL only double the pixel clock. ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel) ver3: Do not set pixel multiplier if transcoder is eDP (Ville) ver4: Macro name change to PIPE_MULT and default else pixel_multiplier Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by:
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