- 09 Jul, 2024 1 commit
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Stephen Boyd authored
Merge tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull more qcom clk driver updates from Bjorn Andersson: - Introduces helper logic to expose clock controllers as simple interconnect providers - Use the interconnect helper above on Qualcomm ipq9574 - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm X1Elite. - Improve error handling in Qualcomm kpss-xcc driver - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const * tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config
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- 08 Jul, 2024 9 commits
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Stephen Boyd authored
There's two problems with shared RCGs. The first problem is that they incorrectly report the parent after commit 703db1f5 ("clk: qcom: rcg2: Cache CFG register updates for parked RCGs"). That's because the cached CFG register value needs to be populated when the clk is registered. clk_rcg2_shared_enable() writes the cached CFG register value 'parked_cfg'. This value is initially zero due to static initializers. If a driver calls clk_enable() before setting a rate or parent, it will set the parent to '0' which is (almost?) always XO, and may not reflect the parent at registration. In the worst case, this switches the RCG from sourcing a fast PLL to the slow crystal speed. The second problem is that the force enable bit isn't cleared. The force enable bit is only used during parking and unparking of shared RCGs. Otherwise it shouldn't be set because it keeps the RCG enabled even when all the branches on the output of the RCG are disabled (the hardware has a feedback mechanism so that any child branches keep the RCG enabled when the branch enable bit is set). This problem wastes power if the clk is unused, and is harmful in the case that the clk framework disables the parent of the force enabled RCG. In the latter case, the GDSC the shared RCG is associated with will get wedged if the RCG's source clk is disabled and the GDSC tries to enable the RCG to do "housekeeping" while powering on. Both of these problems combined with incorrect runtime PM usage in the display driver lead to a black screen on Qualcomm sc7180 Trogdor chromebooks. What happens is that the bootloader leaves the 'disp_cc_mdss_rot_clk' enabled and the 'disp_cc_mdss_rot_clk_src' force enabled and parented to 'disp_cc_pll0'. The mdss driver probes and runtime suspends, disabling the mdss_gdsc which uses the 'disp_cc_mdss_rot_clk_src' for "housekeeping". The 'disp_cc_mdss_rot_clk' is disabled during late init because the clk is unused, but the parent 'disp_cc_mdss_rot_clk_src' is still force enabled because the force enable bit was never cleared. Then 'disp_cc_pll0' is disabled because it is also unused. That's because the clk framework believes the parent of the RCG is XO when it isn't. A child device of the mdss device (e.g. DSI) runtime resumes mdss which powers on the mdss_gdsc. This wedges the GDSC because 'disp_cc_mdss_rot_clk_src' is parented to 'disp_cc_pll0' and that PLL is off. With the GDSC wedged, mdss_runtime_resume() tries to enable 'disp_cc_mdss_mdp_clk' but it can't because the GDSC has wedged all the clks associated with the GDSC causing clks to stay stuck off. This leads to the following warning seen at boot and a black screen because the display driver fails to probe. disp_cc_mdss_mdp_clk status stuck at 'off' WARNING: CPU: 1 PID: 81 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x114/0x168 Modules linked in: CPU: 1 PID: 81 Comm: kworker/u16:4 Not tainted 6.7.0-g0dd3ee31 #1 f5757d475795053fd2ad52247a070cd50dd046f2 Hardware name: Google Lazor (rev1 - 2) with LTE (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : clk_branch_toggle+0x114/0x168 lr : clk_branch_toggle+0x110/0x168 sp : ffffffc08084b670 pmr_save: 00000060 x29: ffffffc08084b680 x28: ffffff808006de00 x27: 0000000000000001 x26: ffffff8080dbd4f4 x25: 0000000000000000 x24: 0000000000000000 x23: 0000000000000000 x22: ffffffd838461198 x21: ffffffd838007997 x20: ffffffd837541d5c x19: 0000000000000001 x18: 0000000000000004 x17: 0000000000000000 x16: 0000000000000010 x15: ffffffd837070fac x14: 0000000000000003 x13: 0000000000000004 x12: 0000000000000001 x11: c0000000ffffdfff x10: ffffffd838347aa0 x9 : 08dadf92e516c000 x8 : 08dadf92e516c000 x7 : 0000000000000000 x6 : 0000000000000027 x5 : ffffffd8385a61f2 x4 : 0000000000000000 x3 : ffffffc08084b398 x2 : ffffffc08084b3a0 x1 : 00000000ffffdfff x0 : 00000000fffffff0 Call trace: clk_branch_toggle+0x114/0x168 clk_branch2_enable+0x24/0x30 clk_core_enable+0x5c/0x1c8 clk_enable+0x38/0x58 clk_bulk_enable+0x40/0xb0 mdss_runtime_resume+0x68/0x258 pm_generic_runtime_resume+0x30/0x44 __genpd_runtime_resume+0x30/0x80 genpd_runtime_resume+0x124/0x214 __rpm_callback+0x7c/0x15c rpm_callback+0x30/0x88 rpm_resume+0x390/0x4d8 rpm_resume+0x43c/0x4d8 __pm_runtime_resume+0x54/0x98 __device_attach+0xe0/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x48/0xa4 device_add+0x52c/0x6fc mipi_dsi_device_register_full+0x104/0x1a8 devm_mipi_dsi_device_register_full+0x28/0x78 ti_sn_bridge_probe+0x1dc/0x2bc auxiliary_bus_probe+0x4c/0x94 really_probe+0xf8/0x270 __driver_probe_device+0xa8/0x130 driver_probe_device+0x44/0x104 __device_attach_driver+0xa4/0xcc bus_for_each_drv+0x94/0xe8 __device_attach+0xf8/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x48/0xa4 deferred_probe_work_func+0x9c/0xd8 Fix these problems by parking shared RCGs at boot. This will properly initialize the parked_cfg struct member so that the parent is reported properly and ensure that the clk won't get stuck on or off because the RCG is parented to the safe source (XO). Fixes: 703db1f5 ("clk: qcom: rcg2: Cache CFG register updates for parked RCGs") Reported-by:
Stephen Boyd <sboyd@kernel.org> Closes: https://lore.kernel.org/r/1290a5a0f7f584fcce722eeb2a1fd898.sboyd@kernel.org Closes: https://issuetracker.google.com/319956935Reported-by:
Laura Nao <laura.nao@collabora.com> Closes: https://lore.kernel.org/r/20231218091806.7155-1-laura.nao@collabora.com Cc: Bjorn Andersson <andersson@kernel.org> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240502224703.103150-1-swboyd@chromium.orgReviewed-by:
Douglas Anderson <dianders@chromium.org> Tested-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Add clk drivers for Qualcomm SM7150 camera, display and video - Add Qualcomm QCM2290 GPU clk driver - Add Qualcomm QCS8386/QCS8084 NSS clk driver - Add Qualcomm SM8650 camera and video drivers - Make qcom_cc_really_probe() take a struct device to allow reuse in non-platform-drivers - Introduce prepare-only branch clock ops in the qcom clk driver to support clocks on buses that take locks - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs - Support Qualcomm Huayra 2290 alpha PLL - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match HS200 support - Add missing PCIe PIPE clocks on Qualcomm IPQ9574 - Fix various configurations and properties in the Qualcomm SA8775P, X1E80100 and SM7280 drivers - Park Qualcomm SM8350 GPU RCGs on XO while disabled - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol - Add missing MODULE_DESCRIPTIONs to some qcom clk drivers * tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (61 commits) clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issue clk: qcom: select right config in CLK_QCM2290_GPUCC definition clk: qcom: Remove QCOM_RPMCC symbol clk: qcom: Add QCM2290 GPU clock controller driver ...
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Varadarajan Narayanan authored
Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240430064214.2030013-6-quic_varada@quicinc.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Varadarajan Narayanan authored
Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Though exposing these as normal clocks would work, having a minimalistic interconnect driver to handle these clocks would make it consistent with other Qualcomm platforms resulting in common code paths. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by:
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Varadarajan Narayanan authored
Wrap icc_clk_register to create devm_icc_clk_register to be able to release the resources properly. Acked-by:
Georgi Djakov <djakov@kernel.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Varadarajan Narayanan authored
Presently, icc-clk driver autogenerates the master and slave ids. However, devices with multiple nodes on the interconnect could have other constraints and may not match with the auto generated node ids. Hence, modify the driver to use the master/slave ids provided by the caller instead of auto generating. Also, update clk-cbf-8996 accordingly. Acked-by:
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Bjorn Andersson authored
Merge the IPQ9574 interconnect binding through a topic branch, to make it possible to use the constants in the DeviceTree source branch as well.
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Satya Priya Kakitapalli authored
SM8150 videocc needs AHB clock, so update the bindings for sm8150 to add the AHB clock. Fixes: df3f61d2 ("dt-bindings: clock: add SM8150 QCOM video clock bindings") Signed-off-by:
Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240509-videocc-sm8150-dt-node-v4-1-e9617f65e946@quicinc.comSigned-off-by:
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Abel Vesa authored
Allow the USB3 second and third GCC PHY pipe clocks to propagate the rate to the pipe clocks provided by the QMP combo PHYs. The first instance is already doing that. Fixes: 161b7c40 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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- 06 Jul, 2024 3 commits
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Varadarajan Narayanan authored
Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Chen Ni authored
Return of_clk_add_hw_provider() in order to transfer the error if it fails. Fixes: 09be1a39 ("clk: qcom: kpss-xcc: register it as clk provider") Signed-off-by:
Chen Ni <nichen@iscas.ac.cn> Reviewed-by:
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Javier Carrasco authored
`lpass_audiocc_sc8280xp_regmap_config` and `lpasscc_sc8280x_regmap_config` are not modified and can be declared as const to move their data to a read-only section. Signed-off-by:
Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by:
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- 02 Jul, 2024 1 commit
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Abel Vesa authored
In case of all pipe clocks, there is a QMP PHY clock that is feeding them. If, for whatever reason, the clock from the PHY is not enabled, halt bit will not get set, and the clock controller driver will assume the clock is stuck in a specific state. The way this is supposed to be properly fixed is to defer the checking of the halt bit until after the PHY clock has been initialized, but doing so complicates the clock controller driver. In fact, since these pipe clocks are consumed by the PHY, while the PHY is also the one providing the source, if clock gets stuck, the PHY driver would be to blame. So instead of checking the halt bit in here, just skip it and assume the PHY driver is handling the source clock correctly. Fixes: 161b7c40 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240628-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v2-1-db3be54b1143@linaro.orgSigned-off-by:
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- 26 Jun, 2024 3 commits
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Chukun Pan authored
The mmc controller of the IPQ6018 does not support HS400 mode. So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). Signed-off-by:
Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cnSigned-off-by:
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Bjorn Andersson authored
Merge SM8650 video and camera clock drivers through topic branch, to make available the DeviceTree binding includes to the DeviceTree source branches as well.
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Jagadeesh Kona authored
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8650 platform. Signed-off-by:
Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by:
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- 25 Jun, 2024 6 commits
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Jagadeesh Kona authored
Add device tree bindings for the camera clock controller on Qualcomm SM8650 platform. Signed-off-by:
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Jagadeesh Kona authored
Update the order of SC8280XP camcc header file in SM8450 camcc bindings. Signed-off-by:
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Jagadeesh Kona authored
Add support to the SM8650 video clock controller by extending the SM8550 video clock controller, which is mostly identical but SM8650 has few additional clocks and minor differences. Signed-off-by:
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Jagadeesh Kona authored
Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a3 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by:
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Jagadeesh Kona authored
SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by:
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Jagadeesh Kona authored
Correct the videocc header file name in SM8450 videocc bindings. Fixes: 1e910b2b ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by:
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- 23 Jun, 2024 7 commits
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Taniya Das authored
Update wait_val fields as per the default hardware values of the GDSC as otherwise it would lead to GDSC FSM state stuck causing power on/off failures of the GSDC. Fixes: 0afa16af ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Also gpu_cc_cb_clk is recommended to be kept always ON, hence use clk_branch2_aon_ops to keep the clock always ON. Fixes: 0afa16af ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
The GPU clocks/GDSCs have been marked critical from the clock driver but the GPU driver votes on these resources as per the HW requirement. In the case where these clocks & GDSCs are left enabled, would have power impact and also cause GPU stability/corruptions. Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON flags for the GPU GDSCs. Fixes: 0afa16af ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
Update the GDSC wait_val fields as per the default hardware values as otherwise they would lead to GDSC FSM state to be stuck and causing failures to power on/off. Also add the GDSC flags as applicable and add support to control PCIE GDSC's using collapse vote registers. Fixes: 08c51ceb ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by:
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Taniya Das authored
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes: 160758b0 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by:
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- 21 Jun, 2024 3 commits
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Luo Jie authored
The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/Signed-off-by:
Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.comSigned-off-by:
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Lukas Bulwahn authored
Commit 8cab0336 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@redhat.com> Fixes: 8cab0336 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by:
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Elliot Berman authored
This symbol is selected by a couple drivers, but isn't used by anyone and hasn't been for years now. Drop it. No functional change intended. Signed-off-by:
Elliot Berman <quic_eberman@quicinc.com> Reviewed-by:
Mike Tipton <quic_mdtipton@quicinc.com> Reviewed-by:
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- 13 Jun, 2024 7 commits
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Konrad Dybcio authored
Add a driver for the GPU clock controller block found on the QCM2290 SoC. Reviewed-by:
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Konrad Dybcio authored
Commit 134b55b7 ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by:
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Bjorn Andersson authored
Merge the QCM2290 GPUCC binding through a topic branch to allow for it to also be merged into the DeviceTree branch.
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Konrad Dybcio authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by:
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Luo Jie authored
The clock controller driver of qca8386/qca8084 is registered as the MDIO device, the hardware register is accessed by MDIO bus that is normally used to access general PHY device, which is different from the current existed qcom clock controller drivers using ioremap to access hardware clock registers, nsscc-qca8k is accessed via an MDIO bus. MDIO bus is commonly utilized by both qca8386/qca8084 and other PHY devices, so the mutex lock mdio_bus->mdio_lock should be used instead of using the mutex lock of remap. To access the hardware clock registers of qca8386/qca8084, there is a special MDIO frame sequence, which needs to be sent to the device. Enable the reference clock before resetting the clock controller, the reference clock rate is fixed to 50MHZ. Reviewed-by:
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Luo Jie authored
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by:
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Luo Jie authored
QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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