- 07 Feb, 2020 11 commits
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Chris Wilson authored
If a request is being re-run after an innocent reset, it is marked as -EAGAIN. So only skip an engine reset if the request is marked as -EIO. Testcase: igt/gem_ctx_exec/basic-nohangcheck Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200207161602.2838218-1-chris@chris-wilson.co.uk
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Mika Kuoppala authored
SIMD16 with Src0 scalar might conflict between Src1/Src2 and cause GRF read issue. Workaround this issue by setting bit 14 in 0xe4f4 which will disable early read/src swap of Src0. Signed-off-by:
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Mika Kuoppala authored
Disable TEDOP clock gating flow by programming 0x20A0[19] = 1 References: HSDES#1407928979 Signed-off-by:
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Chris Wilson authored
We set up a dummy ring in order to measure the size we require for our breadcrumb emission, so that we don't have to manually count dwords! We can pass in the kernel_context to use for this so that if required it is known for the breadcrumb emitter, and we can reuse some details from the kernel_context to reduce the number of temporaries we have to mock. Signed-off-by:
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Chris Wilson authored
Do not try and dereference the i915 private before it has been allocated and attached to the drvdata! Fixes: 7daac72e ("drm/i915/pci: conversion to drm_device based logging macros.") Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200207135048.2788199-1-chris@chris-wilson.co.uk
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Michal Wajdeczko authored
We are sanitizing firmware status and old mmio message, but we forget to sanitize CT status. Fixes: e85de177 ("drm/i915/guc: Introduce guc_is_ready") Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
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Chris Wilson authored
As we may add new waiters to a request as it is being run, we need to mark the list iteration as being safe for concurrent addition. v2: Mika spotted that we used the same trick for signalers_list, so warn the compiler about the lockless walk there as well. Fixes: 32ff621f ("drm/i915/gt: Allow temporary suspension of inflight requests") Signed-off-by:
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Lyude Paul authored
This reverts commit d2a4bb6f. So, turns out that this ended up just breaking things. While many laptops incorrectly advertise themselves as supporting PWM backlight controls, they actually will only work with DPCD backlight controls. Unfortunately, it also seems there are a number of systems which advertise DPCD backlight controls in their eDP DPCD but don't actually support them. Talking with some laptop manufacturers has shown it might be possible to probe this support via the EDID (!?!?) but I haven't been able to confirm that this would work on any other manufacturer's systems. So in the mean time, we'll just revert this commit for now and go back to the old way of doing things. Fixes: d2a4bb6f ("drm/i915: Don't use VBT for detecting DPCD backlight controls") Signed-off-by:
Lyude Paul <lyude@redhat.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Chris Wilson authored
Mika spotted <4>[17436.705441] general protection fault: 0000 [#1] PREEMPT SMP PTI <4>[17436.705447] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 5.5.0+ #1 <4>[17436.705449] Hardware name: System manufacturer System Product Name/Z170M-PLUS, BIOS 3805 05/16/2018 <4>[17436.705512] RIP: 0010:__execlists_submission_tasklet+0xc4d/0x16e0 [i915] <4>[17436.705516] Code: c5 4c 8d 60 e0 75 17 e9 8c 07 00 00 49 8b 44 24 20 49 39 c5 4c 8d 60 e0 0f 84 7a 07 00 00 49 8b 5c 24 08 49 8b 87 80 00 00 00 <48> 39 83 d8 fe ff ff 75 d9 48 8b 83 88 fe ff ff a8 01 0f 84 b6 05 <4>[17436.705518] RSP: 0018:ffffc9000012ce80 EFLAGS: 00010083 <4>[17436.705521] RAX: ffff88822ae42000 RBX: 5a5a5a5a5a5a5a5a RCX: dead000000000122 <4>[17436.705523] RDX: ffff88822ae42588 RSI: ffff8881e32a7908 RDI: ffff8881c429fd48 <4>[17436.705525] RBP: ffffc9000012cf00 R08: ffff88822ae42588 R09: 00000000fffffffe <4>[17436.705527] R10: ffff8881c429fb80 R11: 00000000a677cf08 R12: ffff8881c42a0aa8 <4>[17436.705529] R13: ffff8881c429fd38 R14: ffff88822ae42588 R15: ffff8881c429fb80 <4>[17436.705532] FS: 0000000000000000(0000) GS:ffff88822ed00000(0000) knlGS:0000000000000000 <4>[17436.705534] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[17436.705536] CR2: 00007f858c76d000 CR3: 0000000005610003 CR4: 00000000003606e0 <4>[17436.705538] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 <4>[17436.705540] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 <4>[17436.705542] Call Trace: <4>[17436.705545] <IRQ> <4>[17436.705603] execlists_submission_tasklet+0xc0/0x130 [i915] which is us consuming a partially initialised new waiter in defer_requests(). We can prevent this by initialising the i915_dependency prior to making it visible, and since we are using a concurrent list_add/iterator mark them up to the compiler. Fixes: 8ee36e04 ("drm/i915/execlists: Minimalistic timeslicing") Signed-off-by:
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Chris Wilson authored
Virtual engines are fleeting. They carry a reference count and may be freed when their last request is retired. This makes them unsuitable for the task of housing engine->retire.work so assert that it is not used. Tvrtko tracked down an instance where we did indeed violate this rule. In virtual_submit_request, we flush a completed request directly with __i915_request_submit and this causes us to queue that request on the veng's breadcrumb list and signal it. Leading us down a path where we should not attach the retire. Reported-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: dc93c9b6 ("drm/i915/gt: Schedule request retirement when signaler idles") Signed-off-by:
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Matthew Auld authored
We already have tests that exhaustively exercise the most interesting page-size combinations, along with tests that offer randomisation, and so we should already be testing objects(local, system) with a varying mix of page-sizes, which leaves igt_ppgtt_exhaust_huge providing not much in terms of extra coverage. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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- 06 Feb, 2020 2 commits
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José Roberto de Souza authored
TGL is suffering of timeouts and fifo underruns when disabling transcoder in MST mode, this is fixed by set TRANS_DDI_MODE_SELECT to 0(HDMI mode) when clearing DDI select. Although BSpec disable sequence don't require this step, it is a harmless change and it is also done by Windows driver. Anyhow HW team was notified about that but it can take some time to documentation to be updated. A case that always lead to those issues is: - do a modeset enabling pipe A and pipe B in the same MST stream leaving A as master - disable pipe A, promote B as master doing a full modeset in A - enable pipe A, changing the master transcoder back to A(doing a full modeset in B) - Pow: underruns and timeouts The transcoders involved will only work again when complete disabled and their power wells turned off causing a reset in their registers. v2: Setting TRANS_DDI_MODE_SELECT to default when clearing DDI select not anymore when disabling TRANS_DDI, both work but this one looks more safe. (Ville comment) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200203225549.152301-1-jose.souza@intel.com
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Chris Wilson authored
Always prime the page table registers before starting the ring. Even though we will update these to the per-context page tables during dispatch, it is prudent to ensure that the registers always point to a valid PD. Signed-off-by:
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- 05 Feb, 2020 11 commits
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Chris Wilson authored
Rather than flushing the submission tasklets just before we sleep, flush before we check the request status. Ideally this gives us a moment to process the tasklets after sleeping just before we timeout. v2: Compromise by pushing the flush prior to the timeout, but after the check on completion so that we do not further delay the ready client. Signed-off-by:
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Chris Wilson authored
We have been using '-1' to mean the maximum i915.reset level in the belief that it was unsigned... This turns out to have been a grave error, and instead of setting the default reset mechanism in igt, we have been disabling reset! Signed-off-by:
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Stanislav Lisovskiy authored
Added proper DBuf slice mapping to correspondent pipes, depending on pipe configuration as stated in BSpec. v2: - Remove unneeded braces - Stop using macro for DBuf assignments as it seems to reduce readability. v3: Start using enabled slices mask in dev_priv v4: Renamed "enabled_slices" used in dev_priv to "enabled_dbuf_slices_mask"(Matt Roper) v5: - Removed redundant parameters from intel_get_ddb_size function.(Matt Roper) - Made i915_possible_dbuf_slices static(Matt Roper) - Renamed total_width into total_width_in_range so that it now reflects that this is not a total pipe width but the one in current dbuf slice allowed range for pipe.(Matt Roper) - Removed 4th pipe for ICL in DBuf assignment table(Matt Roper) - Fixed wrong DBuf slice in DBuf table for TGL (Matt Roper) - Added comment regarding why we currently not using pipe ratio for DBuf assignment for ICL v6: - Changed u32 to unsigned int in icl_get_first_dbuf_slice_offset function signature (Ville Syrjälä) - Changed also u32 to u8 in dbuf slice mask structure (Ville Syrjälä) - Switched from DBUF_S1_BIT to enum + explicit BIT(DBUF_S1) access(Ville Syrjälä) - Switched to named initializers in DBuf assignment arrays(Ville Syrjälä) - DBuf assignment arrays now use autogeneration tool from https://patchwork.freedesktop.org/series/70493/ to avoid typos. - Renamed i915_find_pipe_conf to *_compute_dbuf_slices (Ville Syrjälä) - Changed platforms ordering in skl_compute_dbuf_slices to be from newest to oldest(Ville Syrjälä) v7: - Now ORing assigned DBuf slice config always with DBUF_S1 because slice 1 has to be constantly powered on. (Ville Syrjälä) v8: - Added pipe_name for neater printing(Ville Syrjälä) - Renamed width_before_pipe to width_before_pipe_in_range, to better reflect that now all the calculations are happening inside DBuf range allowed by current pipe configuration mask (Ville Syrjälä) - Shortened FIXME comment message, regarding constant ORing with DBUF_S1(Ville Syrjälä) - Added .dbuf_mask named initializer to pipe assignment array (Ville Syrjälä) - Edited pipe assignment array to use only single DBuf slice for gen11 single pipe configurations, until "pipe ratio" thing is finally sorted out(Ville Syrjälä) - Removed unused parameter crtc_state for now(Ville Syrjälä) from icl/tgl_compute_dbuf_slices function Reviewed-by:Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
Start manipulating DBuf slices as a mask, but not as a total number, as current approach doesn't give us full control on all combinations of slices, which we might need(like enabling S2 only can't enabled by setting enabled_slices=1). Removed wrong code from intel_get_ddb_size as it doesn't match to BSpec. For now still just use DBuf slice until proper algorithm is implemented. Other minor code refactoring to get prepared for major DBuf assignment changes landed: - As now enabled slices contain a mask we still need some value which should reflect how much DBuf slices are supported by the platform, now device info contains num_supported_dbuf_slices. - Removed unneeded assertion as we are now manipulating slices in a more proper way. v2: Start using enabled_slices in dev_priv v3: "enabled_slices" is now "enabled_dbuf_slices_mask", as this now sits in dev_priv independently. v4: - Fixed debug print formatting to hex(Matt Roper) - Optimized dbuf slice updates to be used only if slice union is different from current conf(Matt Roper) - Fixed some functions to be static(Matt Roper) - Created a parameterized version for DBUF_CTL to simplify DBuf programming cycle(Matt Roper) - Removed unrequred field from GEN10_FEATURES(Matt Roper) v5: - Removed redundant programming dbuf slices helper(Ville Syrjälä) - Started to use parameterized loop for hw readout to get slices (Ville Syrjälä) - Added back assertion checking amount of DBUF slices enabled after DC states 5/6 transition, also added new assertion as starting from ICL DMC seems to restore the last DBuf power state set, rather than power up all dbuf slices as assertion was previously expecting(Ville Syrjälä) v6: - Now using enum for DBuf slices in this patch (Ville Syrjälä) - Removed gen11_assert_dbuf_enabled and put gen9_assert_dbuf_enabled back, as we really need to have a single unified assert here however currently enabling always slice 1 is enforced by BSpec, so we will have to OR enabled slices mask with 1 in order to be consistent with BSpec, that way we can unify that assertion and against the actual state from the driver, but not some hardcoded value.(concluded with Ville) - Remove parameterized DBUF_CTL version, to extract it to another patch.(Ville Syrjälä) v7: - Removed unneeded hardcoded return value for older gens from intel_enabled_dbuf_slices_mask - this now is handled in a unified manner since device info anyway returns max dbuf slices as 1 for older platforms(Matthew Roper) - Now using INTEL_INFO(dev_priv)->num_supported_dbuf_slices instead of intel_dbuf_max_slices function as it is trivial(Matthew Roper) v8: - Fixed icl_dbuf_disable to disable all dbufs still(Ville Syrjälä) v9: - Renamed _DBUF_CTL_S to DBUF_CTL_S(Ville Syrjälä) - Now using power_domain mutex to protect from race condition, which can occur because intel_dbuf_slices_update might be running in parallel to gen9_dc_off_power_well_enable being called from intel_dp_detect for instance, which causes assertion triggered by race condition, as gen9_assert_dbuf_enabled might preempt this when registers were already updated, while dev_priv was not. Reviewed-by: -
Stanislav Lisovskiy authored
Now start using parameterized DBUF_CTL instead of hardcoded, this would allow shorter access functions when reading or storing entire state. Tried to implement it in a MMIO_PIPE manner, however DBUF_CTL1 address is higher than DBUF_CTL2, which implies that we have to now subtract from base rather than add. v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR macros. Started to use _PICK construct as suggested by Matt Roper. v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice" in macro(Ville Syrjälä) - Introduced enum for enumerating DBUF slices(Ville Syrjälä) Reviewed-by: -
Stanislav Lisovskiy authored
During full modeset, global state(i.e dev_priv) is protected by locking the crtcs in state, otherwise global state is not serialized. Also if it is not a full modeset, we anyway don't need to change DBuf slice configuration as Pipe configuration doesn't change. Reviewed-by:
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Stanislav Lisovskiy authored
Current DBuf slices update wasn't done in proper place, especially its "post" part, which should disable those only once vblank had passed and all other changes are committed. v2: Fix to use dev_priv and intel_atomic_state instead of skl_ddb_values (to be nuked in Villes patch) v3: Renamed "enabled_slices" to "enabled_dbuf_slices_num" (Matt Roper) v4: - Rebase against drm-tip. - Move post_update closer to optimize_watermarks, to prevent unneeded noise from underrun reporting (Ville Syrjälä) Reviewed-by: -
Stanislav Lisovskiy authored
Current consensus that it is redundant as we already have skl_ddb_values struct out there, also this struct contains only single member which makes it unnecessary. v2: As dirty_pipes soon going to be nuked away from skl_ddb_values, evacuating enabled_slices to safer in dev_priv. v3: Changed "enabled_slices" to be "enabled_dbuf_slices_num" (Matt Roper) v4: - Wrapped the line getting number of dbuf slices(Matt Roper) - Removed indeed redundant skl_ddb_values declaration(Matt Roper) Reviewed-by: -
Chris Wilson authored
As only the display codes tries to pin its preallocated framebuffer into an exact location in the GGTT, remove the convenience function and make the pin management explicit in the display code. Then throughout the display management, we track the framebuffer and its plane->vma; with less single purpose code and ready for first class i915_vma. In doing so, this should fix the BUG_ON(vma->pages) on fi-kbl-soraka. Signed-off-by:
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Chris Wilson authored
I am about to stuff more objects into the plane_config and would like to have it clean up after itself. Move the current framebuffer release into a common function so it can be extended with the new object with relative ease. Signed-off-by:
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Jani Nikula authored
The DDI encoder code shouln't have to know about the guts of HDCP. Abstract the pipe update code to a new intel_hdcp_update_pipe() in intel_hdcp.c. No functional changes. Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
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- 04 Feb, 2020 16 commits
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Chris Wilson authored
The current rc6 threshold is larger than the evaluation interval on Ivybridge; it never enters rc6. Remove the special casing so it behaves like the other gen6/gen7, and we see rc6 residencies before we manually park the system. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1114 Testcase: igt/i915_pm_rc6_residency/rc6-idle #ivb Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200203202110.670209-1-chris@chris-wilson.co.uk
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Ville Syrjälä authored
Add the missing comma after the last initialized element of the hpd[] arrays. Best not give people bad ideas. Signed-off-by:
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Ville Syrjälä authored
All the TMDS DVO chips have a sensible looking .detect(). Let's poll them. Signed-off-by:
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Ville Syrjälä authored
ns2501 has a builtin scaler so it doesn't need a fixed mode, but let's still mark it as LVDS instead of TMDS/DVI to make life less confusing. Signed-off-by:
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Ville Syrjälä authored
Let's make sure encoder->hpd_pin and connector->polled are mirror images of each other (when we want to use polling). The other potentially polled connectors (sdvo and tv) already get this right. Also nuke the redundant force_hotplug_required initialization (the thing is kzalloc()ed). Signed-off-by:
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Ville Syrjälä authored
Simplify the hotplug code connector->encoder->hpd_pin handling by introducing a helper for exactly this purpose. In the helper we can neatly deal with the potential lack of an attached encoder on fresh MST connectors leaving the rest of the hpd code oblivious to such details. Cc: Lyude Paul <lyude@redhat.com> Signed-off-by:
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Chris Wilson authored
drm_pci_alloc and drm_pci_free are just very thin wrappers around dma_alloc_coherent, with a note that we should be removing them. Furthermore since commit de09d31d Author: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Date: Fri Jan 15 16:51:42 2016 -0800 page-flags: define PG_reserved behavior on compound pages As far as I can see there's no users of PG_reserved on compound pages. Let's use PF_NO_COMPOUND here. drm_pci_alloc has been declared broken since it mixes GFP_COMP and SetPageReserved. Avoid this conflict by weaning ourselves off using the abstraction and using the dma functions directly. Reported-by: Taketo Kabe Closes: https://gitlab.freedesktop.org/drm/intel/issues/1027 Fixes: de09d31d ("page-flags: define PG_reserved behavior on compound pages") Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20200202153934.3899472-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Lift the routines to emit a request to update the SSEU on the intel_context out of i915_gem_context. Signed-off-by:
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Chris Wilson authored
Shrink the strncpy bounds to ensure the NUL-terminator can fit within the embedded array: In file included from drivers/gpu/drm/i915/gem/i915_gem_context.c:2475: drivers/gpu/drm/i915/gem/selftests/mock_context.c: In function ‘mock_context’: drivers/gpu/drm/i915/gem/selftests/mock_context.c:40:3: error: ‘strncpy’ specified bound 24 equals destination size [-Werror=stringop-truncation] 40 | strncpy(ctx->name, name, sizeof(ctx->name)); Signed-off-by:
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Chris Wilson authored
Exercise the seqno wrap paths on the kernel context to provide a small amount of sanity checking and ensure that they are visible to lockdep. Signed-off-by:
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Chris Wilson authored
To write to the DISPLAY_PHY_CONTROL requires holding the powerwells, which during early resume we have not yet acquired until later in intel_display_power_init_hw(). So compute the initial chv_phy_control, but leave the HW unset until we first acquire the powerwell. <7> [120.055984] i915 0000:00:02.0: [drm:intel_power_domains_init_hw [i915]] rawclk rate: 200000 kHz <4> [120.056381] ------------[ cut here ]------------ <4> [120.056621] i915 0000:00:02.0: Unclaimed write to register 0x1e0100 <4> [120.056924] WARNING: CPU: 1 PID: 164 at drivers/gpu/drm/i915/intel_uncore.c:1166 __unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.056935] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl btbcm btintel i915 bluetooth coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg snd_hda_codec ghash_clmulni_intel snd_hwdep ecdh_generic ecc snd_hda_core r8169 snd_pcm lpc_ich realtek pinctrl_cherryview i2c_designware_pci prime_numbers <4> [120.057027] CPU: 1 PID: 164 Comm: kworker/u4:3 Tainted: G U 5.5.0-CI-CI_DRM_7854+ #1 <4> [120.057038] Hardware name: /NUC5CPYB, BIOS PYBSWCEL.86A.0055.2016.0812.1130 08/12/2016 <4> [120.057058] Workqueue: events_unbound async_run_entry_fn <4> [120.057275] RIP: 0010:__unclaimed_reg_debug+0x69/0x80 [i915] <4> [120.057289] Code: 48 8b 78 18 48 8b 5f 50 48 85 db 74 2d e8 1f a0 3f e1 45 89 e8 48 89 e9 48 89 da 48 89 c6 48 c7 c7 00 8c 48 a0 e8 67 82 df e0 <0f> 0b 83 2d ce e2 2b 00 01 5b 5d 41 5c 41 5d c3 48 8b 1f eb ce 66 <4> [120.057301] RSP: 0018:ffffc90000bcfd08 EFLAGS: 00010082 <4> [120.057315] RAX: 0000000000000000 RBX: ffff888079919b60 RCX: 0000000000000003 <4> [120.057326] RDX: 0000000080000003 RSI: 0000000000000000 RDI: 00000000ffffffff <4> [120.057336] RBP: ffffffffa04c9f4e R08: 0000000000000000 R09: 0000000000000001 <4> [120.057348] R10: 0000000025c3d560 R11: 000000006815f798 R12: 0000000000000000 <4> [120.057359] R13: 00000000001e0100 R14: 0000000000000286 R15: ffffffff8234a76b <4> [120.057371] FS: 0000000000000000(0000) GS:ffff888074b00000(0000) knlGS:0000000000000000 <4> [120.057382] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [120.057393] CR2: 000055f4197df0d8 CR3: 000000006f326000 CR4: 00000000001006e0 <4> [120.057404] Call Trace: <4> [120.057635] fwtable_write32+0x114/0x1d0 [i915] <4> [120.057892] intel_power_domains_init_hw+0x4ff/0x650 [i915] <4> [120.058150] intel_power_domains_resume+0x3d/0x70 [i915] <4> [120.058363] i915_drm_resume_early+0x97/0xd0 [i915] <4> [120.058575] ? i915_resume_switcheroo+0x30/0x30 [i915] <4> [120.058594] dpm_run_callback+0x64/0x280 <4> [120.058626] device_resume_early+0xa7/0xe0 <4> [120.058652] async_resume_early+0x14/0x40 v2: Write our expected value of DISPLAY_PHY_CONTROL during sync_hw, so that it should always match the driver state after resume. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1089Signed-off-by:
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Chris Wilson authored
[ 23.419442] BUG: KASAN: null-ptr-deref in intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.419527] Read of size 4 at addr 00000000000000f8 by task insmod/735 [ 23.419578] [ 23.419644] CPU: 2 PID: 735 Comm: insmod Not tainted 5.5.0+ #114 [ 23.419716] Hardware name: ��������������������������������� ���������������������������������/���������������������������������, BIOS RYBDWi35.86A.0246.2 [ 23.419793] Call Trace: [ 23.419864] dump_stack+0xef/0x16e [ 23.419927] __kasan_report.cold+0x60/0x90 [ 23.420157] ? intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.420397] intel_plane_calc_min_cdclk+0x82/0x440 [i915] [ 23.420630] intel_atomic_check+0x455f/0x65a0 [i915] [ 23.420708] ? mark_held_locks+0x90/0x90 [ 23.420929] ? intel_crtc_duplicate_state+0x2e/0x1b0 [i915] [ 23.421172] ? intel_plane_duplicate_state+0x2d/0xc0 [i915] [ 23.421239] ? __drm_dbg+0xa4/0x120 [ 23.421303] ? __kasan_kmalloc.constprop.0+0xc2/0xd0 [ 23.421355] ? __kmalloc_track_caller+0x23a/0x320 [ 23.421602] ? intel_calc_active_pipes+0x1c0/0x1c0 [i915] [ 23.421852] sanitize_watermarks+0x220/0x510 [i915] [ 23.422092] ? intel_atomic_check+0x65a0/0x65a0 [i915] [ 23.422164] ? drm_modeset_unlock_all+0x88/0x130 [ 23.422402] intel_modeset_init+0x1b76/0x3c90 [i915] [ 23.422647] ? intel_finish_reset+0x2d0/0x2d0 [i915] [ 23.422851] ? intel_irq_install+0x12c/0x210 [i915] [ 23.423076] i915_driver_probe+0x13e7/0x2930 [i915] v2: No crtc is implied by an invisible plane, so the extra !crtc check is redundant. Signed-off-by:
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Chris Wilson authored
If the display is not driving any pipes, we cannot change the bclk and doing so risks chasing NULL pointers: <6> [278.907105] snd_hda_intel 0000:00:0e.0: DSP detected with PCI class/subclass/prog-if info 0x040100 <6> [278.909936] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) <7> [278.910078] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2 <1> [278.910228] BUG: kernel NULL pointer dereference, address: 0000000000000080 <1> [278.910243] #PF: supervisor read access in kernel mode <1> [278.910251] #PF: error_code(0x0000) - not-present page <6> [278.910260] PGD 0 P4D 0 <4> [278.910267] Oops: 0000 [#1] PREEMPT SMP PTI <4> [278.910276] CPU: 0 PID: 5 Comm: kworker/0:0 Tainted: G U 5.5.0-CI-CI_DRM_7853+ #1 <4> [278.910289] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS GELKRVPA.X64.0062.B30.1708222146 08/22/2017 <4> [278.910312] Workqueue: events azx_probe_work [snd_hda_intel] <4> [278.910327] RIP: 0010:__ww_mutex_lock.constprop.15+0x5e/0x1090 <4> [278.910338] Code: 75 88 be a7 03 00 00 65 48 8b 04 25 28 00 00 00 48 89 45 c8 31 c0 4c 89 c3 e8 5e b3 6d ff 44 8b 3d 2f 24 37 02 45 85 ff 75 0a <4d> 3b 6d 58 0f 85 3f 07 00 00 48 85 db 74 22 49 8b 95 80 00 00 00 <4> [278.910362] RSP: 0018:ffffc9000008bc10 EFLAGS: 00010246 <4> [278.910371] RAX: 0000000000000246 RBX: ffffc9000008bd30 RCX: 0000000000000001 <4> [278.910382] RDX: 0000000000000000 RSI: ffffffff82647c60 RDI: ffff88817b27d848 <4> [278.910393] RBP: ffffc9000008bcc0 R08: 0000000000000000 R09: 0000000000000001 <4> [278.910404] R10: ffffc9000008bce0 R11: 0000000000000000 R12: ffffffff8168f0fc <4> [278.910414] R13: 0000000000000028 R14: ffffc9000008bd60 R15: 0000000000000000 <4> [278.910425] FS: 0000000000000000(0000) GS:ffff88817bc00000(0000) knlGS:0000000000000000 <4> [278.910437] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [278.910446] CR2: 0000000000000080 CR3: 00000001650da000 CR4: 0000000000340ef0 <4> [278.910456] Call Trace: <4> [278.910468] ? mark_held_locks+0x49/0x70 <4> [278.910479] ? ww_mutex_lock+0x39/0x70 <4> [278.910487] ww_mutex_lock+0x39/0x70 <4> [278.910497] drm_modeset_lock+0x6c/0x120 <4> [278.910575] glk_force_audio_cdclk+0x7d/0x140 [i915] <4> [278.910656] i915_audio_component_get_power+0xf2/0x110 [i915] <4> [278.910673] snd_hdac_display_power+0x7d/0x120 [snd_hda_core] <4> [278.910686] azx_probe_work+0x88/0x7e0 [snd_hda_intel] v2: Reorder glk_force_audio_cdclk() parameters to fit in with the norm. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1095Signed-off-by:
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Wambui Karuga authored
Manual conversion of instances of printk based drm logging macros to the struct drm_device based logging macros in i915/i915_pci.c. Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
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Wambui Karuga authored
Manually convert printk based drm logging macros to the struct drm_device based logging macros in i915/i915_cmd_parser.c. This also involves extracting the drm_i915_private device from various intel types for use in the macros. Instances of the DRM_DEBUG macro are not converted due to the lack of a similar struct drm_device based logging macro. References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.htmlSigned-off-by:
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Wambui Karuga authored
Manual conversion of printk based logging macros to the struct drm_device based logging macros in i915/i915_debugfs.c. Also involves extracting the struct drm_i915_private device from various intel types to use in the macros. This does not convert various instances of the DRM_DEBUG macro due to the lack of an analogous struct drm_device based logging macro. References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.htmlSigned-off-by:
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