- 15 Jun, 2022 1 commit
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Yang Wang authored
issue calltrace: [ 402.773695] [drm] failed to load ucode SMC(0x2C) [ 402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0) [ 402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed! [ 402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring [ 402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed [ 402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22 [ 402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed [ 402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init if not reset mp1 state during kernel driver unload, it will cause psp load pmfw fail at the second time. add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7 Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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- 10 Jun, 2022 13 commits
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Kenneth Feng authored
support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO for the low latency, and it only happens on specific platforms. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Kenneth Feng authored
enable gfxoff on smu_v13_0_7 Signed-off-by:
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Kenneth Feng authored
update the driver if header for smu_v13_0_7 Signed-off-by:
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Andrey Grodzovsky authored
We skip rest requests if another one is already in progress. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by:
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Andrey Grodzovsky authored
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by:
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Andrey Grodzovsky authored
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by:
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Andrey Grodzovsky authored
Save the extra usless work schedule. Signed-off-by:
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Andrey Grodzovsky authored
Will be read by executors of async reset like debugfs. Signed-off-by:
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Andrey Grodzovsky authored
This reverts commit 6417250d. amdpgu need this function in order to prematurly stop pending reset works when another reset work already in progress. Acked-by:
Tejun Heo <tj@kernel.org> Signed-off-by:
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Ramesh Errabolu authored
The field is redundant and does not serve any functional role Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Chandan Vurdigere Nataraj authored
[Why] Getting below build errors: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1419:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1535:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:3276:20: error: variable 'v1_5' is uninitialized when used here [-Werror,-Wuninitialized] for (i = 0; i < v1_5->number_of_path; ++i) ^~~~ [How] Fix compilation issues Signed-off-by:Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Chandan Vurdigere Nataraj authored
[Why] Getting below errors: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1414:5: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] mode_lib->vba.SourceScan[k], ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1744:22: error: implicit conversion from enumeration type 'enum scan_direction_class' to different enumeration type 'enum dm_rotation_angle' [-Werror,-Wenum-conversion] && (!(!IsVertical(mode_lib->vba.SourceScan[k])) || mode_lib->vba.DCCEnable[k] == true)) { ~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 errors generated. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.c:5484:18: error: implicit conversion from enumeration type 'RequestType' to different enumeration type 'enum RequestType' [-Werror,-Wenum-conversion] RequestLuma = REQ_256Bytes; ~ ^~~~~~~~~~~~ 18 errors of similar kind [How] 1. Add typecast at relevant places 2. Move the enum RequestType definition ahead of declarations Signed-off-by:
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- 08 Jun, 2022 26 commits
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Christian König authored
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146 ("drm/amdgpu: rework TLB flushing") Reviewed-by:
Michal Kubecek <mkubecek@suse.cz> Signed-off-by:
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Christian König authored
The job is not yet initialized here. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Kenneth Feng authored
enable BACO on smu_v13_0_7 Signed-off-by:
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Kenneth Feng authored
add interface to deallocate power_context for smu_v13_0_7 Signed-off-by:
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Mohammad Zafar Ziya authored
Add jpeg vmid update under IB submit Signed-off-by:
Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Yifan Zhang authored
invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0 Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Evan Quan authored
PMFW will handle that properly. Driver involvement may cause some unexpected issues. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Drop those redundant declarations in smu_v13_0.h. Signed-off-by:
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Evan Quan authored
Fulfill the interfaces for mode1 reset related. Signed-off-by:
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Evan Quan authored
Make sure the clockgating feature is supported before action. Otherwise, the feature may be disabled unexpectedly on enablement request. Signed-off-by:
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Evan Quan authored
Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by:
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Evan Quan authored
Drop extra CMN2ASIC_MAPPING_FEATURE transform. Also some cosmetic fixes for better readability. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
As there is actually no direct dependence between them. Signed-off-by:
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Evan Quan authored
The new 78.40.0 PMFW has this feature supported. Signed-off-by:
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ZhenGuo Yin authored
The scratch register should be accessed through MMIO instead of RLCG in SRIOV, since it being used in RLCG register access function. Fixes: d54762cc ("drm/amdgpu: nuke dynamic gfx scratch reg allocation") Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Reviewed-by:
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Xiaohui Zhang authored
Similar to the handling of amdgpu_sa_bo_next_hole in commit 6a15f3ff ("drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole"), we thought a patch might be needed here as well. The entries were only initialized once in radeon_sa_bo_new. If a fence wasn't signalled yet in the first radeon_sa_bo_next_hole call, but then got signalled before a later radeon_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in radeon_sa_bo_new. Signed-off-by:
Xiaohui Zhang <xiaohuizhang@ruc.edu.cn> Signed-off-by:
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Felix Kuehling authored
Removed an unused parameter from two functions and added kernel-doc comments. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
GCC throw warnings for the function dcn21_update_bw_bounding_box and dcn316_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Ramesh Errabolu authored
Extend KFD device topology to surface peer-to-peer links among GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is REQUIRED to surface peer-to-peer links. Prior to this KFD did not expose to user mode any P2P links or indirect links that go over two or more direct hops. Old versions of the Thunk used to make up their own P2P and indirect links without the information about peer-accessibility and chipset support available to the kernel mode driver. In this patch we expose P2P links in a new sysfs directory to provide more reliable P2P link information to user mode. Old versions of the Thunk will continue to work as before and ignore the new directory. This avoids conflicts between P2P links exposed by KFD and P2P links created by the Thunk itself. New versions of the Thunk will use only the P2P links provided in the new p2p_links directory, if it exists, or fall back to the old code path on older KFDs that don't expose p2p_links. Signed-off-by:
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Xiaohui Zhang authored
Similar to the handling of amdgpu_mode_dumb_create in commit 54ef0b54 ("drm/amdgpu: integer overflow in amdgpu_mode_dumb_create()"), we thought a patch might be needed here as well. args->size is a u64. arg->pitch and args->height are u32. The multiplication will overflow instead of using the high 32 bits as intended. Signed-off-by:
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Alex Deucher authored
This is the same as the default case, so drop the extra logic. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
GCC throw warnings for the function dcn31_update_bw_bounding_box and dcn316_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box due to its frame size that looks like this: error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] For fixing this issue I dropped an intermadiate variable. Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why] 0 was passed in place of a pointer which triggered null pointer dereference. Causes a backtrace like: [ 41.159466] RIP: 0010:dccg31_set_audio_dtbclk_dto+0x10/0x120 [amdgpu] [ 41.159928] Code: c0 00 00 00 6a 01 8b 92 84 01 00 00 52 0f b6 40 61 e9 30 ff ff ff 0f 1f 40 00 0f 1f 44 00 00 55 48 89 e5 41 56 41 55 41 54 53 <44> 8b 66 18 48 89 fb 48 8b 47 30 48 8b 3f 45 85 e4 74 09 4c 63 6e [ 41.159932] RSP: 0018:ffffaee54055afd0 EFLAGS: 00010246 [ 41.159936] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff917445901800 [ 41.159939] RDX: ffffffffc15e6ca0 RSI: 0000000000000000 RDI: ffff91744dbd8c60 [ 41.159941] RBP: ffffaee54055aff0 R08: 0000000000000100 R09: ffffaee54055afe8 [ 41.159944] R10: 0000000000000001 R11: 0000000000000009 R12: ffff91747ca201f0 [ 41.159946] R13: ffff91747ca20000 R14: ffff917448720438 R15: ffff91747ca20000 [ 41.159948] FS: 00007f5e13e5f740(0000) GS:ffff91775ca40000(0000) knlGS:0000000000000000 [ 41.159951] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 41.159954] CR2: 0000000000000018 CR3: 000000010fea0000 CR4: 00000000003506e0 [ 41.159956] Call Trace: [ 41.159959] <TASK> [ 41.159964] dce110_setup_audio_dto.isra.0+0xd8/0x1f0 [amdgpu] [ 41.160411] dce110_apply_ctx_to_hw+0x1aa/0x780 [amdgpu] [ 41.160842] ? __free_pages+0x88/0xb0 [ 41.160850] ? kfree+0x360/0x3e0 [ 41.160857] dc_commit_state+0x337/0xac0 [amdgpu] [ 41.161135] amdgpu_dm_atomic_commit_tail+0x5e3/0x2680 [amdgpu] [How] Pass in a pointer that contains nullified parameters instead of null pointer. Fixes: 405bb9ee ("drm/amd/display: Implement DTBCLK ref switching on dcn32") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Ramesh Errabolu authored
Add support for peer-to-peer communication among AMD GPUs over PCIe bus. Support REQUIRES enablement of config HSA_AMD_P2P. Signed-off-by:
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Ramesh Errabolu authored
Extend current kernel config requirements of amdgpu by adding config HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer communication between AMD GPU devices over PCIe bus Signed-off-by:
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