- 16 Jul, 2018 39 commits
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Stefan Agner authored
In the uSDHC case (e.g. i.MX 6) clocks only get disabled if frequency is set to 0. However, it could be that the stack asks for a frequency change while clocks are on. In that case the function clears the divider registers (by clearing ESDHC_CLOCK_MASK) while the clock is enabled! This causes a short period of time where the clock is undivided (on a i.MX 6DL a clock of 196MHz has been measured). For older IP variants the driver disables clock by clearing some bits in ESDHC_SYSTEM_CONTROL. Make sure to disable card clock before changing frequency for uSDHC IP variants too. Signed-off-by:
Stefan Agner <stefan@agner.ch> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Stefan Agner authored
It seems that SD3.0 advertisement needs to be set for higher eMMC speed modes (namely DDR52) as well. The TRM states that the SD3.0 advertisement bit should be set for all controller instances, even for those not supporting UHS-I mode... When specifying vqmmc-supply as a fixed 1.8V regulator on a Tegra SD/MMC instance which is connected to a eMMC device, the stack enables SD3.0. However, enabling it has consequences: If SDHCI 3.0 support is advertised the stack enables Auto-CMD23. Unfortunately Auto-CMD23 seems not to work well with Tegra 3 currently. It leads to regular warnings: mmc2: Got command interrupt 0x00010000 even though no command operation was in progress. It is not entirely clear why those errors happens. It seems that a Linux 3.1 based downstream kernel which has Auto-CMD23 support does not show those warnings. Use quirk SDHCI_QUIRK2_ACMD23_BROKEN to prevent Auto-CMD23 being used for now. With this the eMMC works stable on high-speed mode while still announcing SD3.0. This allows to use mmc-ddr-1_8v to enables DDR52 mode. In DDR52 mode read speed improves from about 42MiB/s to 72MiB/s on an Apalis T30. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by:
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Stefan Agner authored
Make sure the clock is doubled when using eMMC DDR52 mode. Signed-off-by:
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Stefan Agner authored
The stack assumes that SDHC controller which support SD3.0 (SDR104) do support HS200. This is not the case for Tegra 3, which does support SD 3.0 but only supports eMMC spec 4.41. Use SDHCI_QUIRK2_BROKEN_HS200 to indicate that the controller does not support HS200. Note that commit 156e14b1 ("mmc: sdhci: fix caps2 for HS200") added the tie between SD3.0 (SDR104) and HS200. I don't think that this is necessarly true. It is fully legitimate to support SD3.0 and not support HS200. The quirk naming suggests something is broken in the controller, but this is not the case: The controller simply does not support HS200. Fixes: 7ad2ed1d ("mmc: tegra: enable UHS-I modes") Signed-off-by:
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Prabu Thangamuthu authored
Synopsys has DWC MSHC controller on HPAS-DX platform connected using PCIe interface with SD card slot and eMMC device slots. This patch is to enable SD cards connected on this platform. As Clock generation logic is implemented using MMCM module of HAPS-DX platform, we have separate functions to control the MMCM to generate required clocks with respect to speed mode. Signed-off-by:
Prabu Thangamuthu <prabu.t@synopsys.com> Acked-by:
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Fabio Estevam authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Jisheng Zhang authored
Add a driver for SDHCI OF Synopsys DesignWare Cores Mobile Storage Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
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Jisheng Zhang authored
Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host Controller can support eMMC/SD/SDIO. Add the bindings. Signed-off-by:
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Stefan Agner authored
For eMMC devices it is valid to only support 1.8V signaling. When vqmmc is set to a fixed 1.8V regulator the stack tries to set 3.3V initially and prints the following warning: mmc1: Switching to 3.3V signalling voltage failed Clear the MMC_SIGNAL_VOLTAGE_330 flag in case 3.3V is signaling is not available. This prevents the stack from even trying to use 3.3V signaling and avoids the above warning. Signed-off-by:
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Laurentiu Tudor authored
SDHCI controller in ls1043a and ls1046a generate 40-bit wide addresses when doing DMA. Make sure that the corresponding dma mask is correctly configured. Context: when enabling smmu on these chips the following problem is encountered: the smmu input address size is 48 bits so the dma mappings for sdhci end up 48-bit wide. However, on these chips sdhci only use 40-bits of that address size when doing dma. So you end up with a 48-bit address translation in smmu but the device generates transactions with clipped 40-bit addresses, thus smmu context faults are triggered. Setting up the correct dma mask fixes this situation. Signed-off-by:
Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by:
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weiyongjun (A) authored
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 2 was used: -Wimplicit-fallthrough=2 Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Daniel Mack authored
Just a cosmetic cleanup with no functional impact. Signed-off-by:
Daniel Mack <daniel@zonque.org> Signed-off-by:
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Daniel Mack authored
A recent commit introduced a call to mmc_of_parse() and removed the explicit assignment of GPIOs in the pdata structure. This will leave them set to 0, which is a valid GPIO per se, so the code that looks at these members will try to allocate them and fail. To fix this properly, make the following changes: a) Refrain from allocating and assiging a pdata struct from pxamci_of_init(). It's a hack to do it this way anyway. Instead, move the only remaining member of interest in 'struct pxamci_host' and assign the value from either the passed in pdata pointer or with the value read from DT. b) Let the only user of 'detect_delay_ms' look at the member of 'struct pxamci_host', not the pdata. c) Make more code in pxamci_probe() dependent on the presence of actual pdata. This will also ease the removal of pdata one day. Signed-off-by:
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Daniel Mack authored
Strip some code by letting the mmc core handle the regulators. The old .gpio_power pdata handling is kept around for now. This also set the voltage on the regulator and handles -EPROBE_DEFER correctly. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Daniel Mack authored
Devicetree-enabled boards should use proper regulators to control the power of cards, not GPIOs, so let's remove this property. The regulator properties are supported by the MMC core and are described in the generic MMC document: Documentation/devicetree/bindings/mmc/mmc.txt Note that devicetree support for PXA platforms hasn't fully landed yet, so this binding does not have any users at this point. Signed-off-by:
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Daniel Mack authored
Call into mmc_of_parse() from pxamci_of_init(). As it needs a pointer to a struct mmc_host, refactor the code a bit. This allows all generic MMC properties to be set that are described in Documentation/devicetree/bindings/mmc/mmc.txt. Reword the documentation a bit to make that clear. The "cd" and "wp" gpio lookups are removed as the lookup will now be done by mmc_of_parse(). Signed-off-by:
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Daniel Mack authored
pxamci_of_init() had some weird indenting. Signed-off-by:
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Daniel Mack authored
These gpio assignments don't make sense, as they are not used anywhere. Remove the dead code. Signed-off-by:
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Daniel Mack authored
These members are no longer in use, so let's remove them. Signed-off-by:
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Daniel Mack authored
This seems to be a left-over from times before the IRQ was handled by devm functions. Remove it. Signed-off-by:
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Stefan Agner authored
The field support_vsel is currently only used in the device tree case. Get rid of it. No change in behavior. Signed-off-by:
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Stefan Agner authored
The uSDHC supports DDR modes for eMMC devices running at 3.3V. This allows to run eMMC with 3.3V signaling voltage at DDR52 mode: # cat /sys/kernel/debug/mmc1/ios clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 0 (3.30 V) driver type: 0 (driver type B) Signed-off-by:
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Ulf Hansson authored
The last user of mmc_power_save|restore_host() APIs is gone, hence let's drop them. Drop also the corresponding bus_ops callback, ->power_save|restore() as those becomes redundant. Cc: Tony Lindgren <tony@atomide.com> Cc: Eyal Reizer <eyalreizer@gmail.com> Signed-off-by: -
yinbo.zhu authored
Convert to use of_match_node method to fix up eSDHC clock for ls1046a/ls1012a/p1010. Also add eSDHC clock fixup for ls1021a according to its datasheet. The maxmum speed for ls1021a eSDHC high speed mode is 46.5MHz. Signed-off-by:
Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by:
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Helmut Grohne authored
Some controllers immediately report SDHCI_CLOCK_INT_STABLE after enabling the clock even when the clock is not stable. When used in conjunction with older/slower cards, this can result in: mmc0: error -84 whilst initialising SD card When the stable reporting is known to be broken, we simply wait for the maximum stabilization period. Signed-off-by:Helmut Grohne <h.grohne@intenta.de> Acked-by:
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Helmut Grohne authored
Some controllers immediately report that their internal clock is stable after activating it even when the clock is not stable. When used in conjunction with older/slower cards, this can result in: mmc0: error -84 whilst initialising SD card This flag allows documenting and thus working around such a hardware defect. Signed-off-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Adrian Hunter authored
Add PCI Ids for Intel ICP. Signed-off-by:
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Sayali Lokhande authored
Add support to use the new compatible string "qcom,sdhci-msm-v5". Based on the msm variant, pick the relevant variant data and use it for register read/write to msm specific registers. Signed-off-by:
Sayali Lokhande <sayalil@codeaurora.org> Signed-off-by:
Vijay Viswanath <vviswana@codeaurora.org> Reviewed-by:
Evan Green <evgreen@chromium.org> Signed-off-by:
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Sayali Lokhande authored
For SDCC version 5.0.0 and higher, new compatible string "qcom,sdhci-msm-v5" is added. Signed-off-by:
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Vijay Viswanath authored
In addition to offsets of certain registers changing, the registers in core_mem have been shifted to HC mem as well. To access these registers, define msm version specific functions. These functions can be loaded into the function pointers at the time of probe based on the msm version detected. Also defind new data structure to hold version specific Ops and register addresses. Signed-off-by:
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Sayali Lokhande authored
For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. Define a new data structure where we can statically define the address offsets for the registers in different SDCC versions. Signed-off-by:
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Masaharu Hayakawa authored
This patch adds processing for selecting HS400 mode. Signed-off-by:
Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Masaharu Hayakawa authored
This patch adds processing for selecting HS400 mode. Signed-off-by:
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Simon Horman authored
This adds two new HS400 tuning operations: * hs400_downgrade * hs400_complete These supplement the existing HS400 operation: * prepare_hs400_tuning This is motivated by a requirement of Renesas SDHI for the following: 1. Disabling SCC before selecting to HS if selection of HS400 has occurred. This can be done in an implementation of prepare_hs400_tuning_downgrade 2. Updating registers after switching to HS400 This can be done in an implementation of complete_hs400_tuning If hs400_downgrade or hs400_complete are not implemented then they are not called. Thus means there should be no affect for existing drivers as none implemt these ops. Signed-off-by:
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Marek Szyprowski authored
dw_mci_exynos_resume_noirq() performs DWMMC register access without ensuring that respective clocks are enabled. This might cause external abort on some systems (observed on Exynos5433 based boards). Fix this by forcing a PM runtime active state before register access. Using SET_NOIRQ_SYSTEM_SLEEP_PM_OPS allows also to cleanup conditional code a bit. Suggested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
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Aapo Vienamo authored
The sdhci get_max_clock callback is set to sdhci_pltfm_clk_get_max_clock and tegra_sdhci_get_max_clock is removed. It appears that the shdci-tegra specific callback was originally introduced due to the requirement that the host clock has to be twice the bus clock on DDR50 mode. As far as I can tell the only effect the removal has on DDR50 mode is in cases where the parent clock is unable to supply the requested clock rate, causing the DDR50 mode to run at a lower frequency. Currently the DDR50 mode isn't enabled on any of the SoCs and would also require configuring the SDHCI clock divider register to function properly. The problem with tegra_sdhci_get_max_clock is that it divides the clock rate by two and thus artificially limits the maximum frequency of faster signaling modes which don't have the host-bus frequency ratio requirement of DDR50 such as SDR104 and HS200. Furthermore, the call to clk_round_rate() may return an error which isn't handled by tegra_sdhci_get_max_clock. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Tested-by:
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Shawn Lin authored
R1_STATUS(x) now is only used by ioctl_rpmb_card_status_poll(), which checks all bits as possible. But according to the spec, bit 17 and bit 18 should be ignored, as well bit 14 which is reserved(must be set to 0) quoting from the spec and these rule apply to all places checking the device status. So change its checking from 0xFFFFE000 to 0xFFF9A000. As a bonus, we reuse it for mmc_do_erase() as well as mmc_switch_status_error(). (1) Currently mmc_switch_status_error() doesn't check bit 25, but it means device is locked but not unlocked by CMD42 prior to any operations which need check busy, which is also not allowed. (2) mmc_do_erase() also forgot to to check bit 15, WP_ERASE_SKIP. The spec says "Only partial address space was erased due to existing write protected blocks.", which obviously means we should fail this I/O. Otherwise, the partial erased data stored in nonvalatile flash violates the data integrity from the view of I/O owner, which probably confuse it when further used. So reusing R1_STATUS for them not only improve the readability but also slove real problems. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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Ulf Hansson authored
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- 15 Jul, 2018 1 commit
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Linus Torvalds authored
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