- 05 Jul, 2022 8 commits
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Rahul T R authored
Add compatible to support dphy tx on j721e Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220623125433.18467-2-r-ravikumar@ti.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Peter Geis authored
If a phy supply is designated but isn't available at probe time, an EPROBE_DEFER is returned. Use dev_err_probe to prevent this from incorrectly printing during boot. Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.comSigned-off-by:
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Jiang Jian authored
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c line: 139 * when in RxULPS check state, after the the logic enable the analog, changed to * when in RxULPS check state, after the logic enable the analog, Signed-off-by:
Jiang Jian <jiangjian@cdjrlc.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220621120015.113682-1-jiangjian@cdjrlc.comSigned-off-by:
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Vidya Sagar authored
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by:
Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20220629060435.25297-9-vidyas@nvidia.comSigned-off-by:
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Vidya Sagar authored
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220629060435.25297-2-vidyas@nvidia.comSigned-off-by:
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Jianjun Wang authored
Add PCIe GEN3 PHY driver support on MediaTek chipsets. Signed-off-by:
Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
AngeloGioachino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220617070246.20142-3-jianjun.wang@mediatek.comSigned-off-by:
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Jianjun Wang authored
Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
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Andy Shevchenko authored
On some platforms, like Intel Merrifield, the writing values during power on may timeout: tusb1210 dwc3.0.auto.ulpi: error -110 writing val 0x41 to reg 0x80 phy phy-dwc3.0.auto.ulpi.0: phy poweron failed --> -110 dwc3 dwc3.0.auto: error -ETIMEDOUT: failed to initialize core dwc3: probe of dwc3.0.auto failed with error -110 which effectively fails the probe of the USB controller. Drop the check as it was before the culprit commit (see Fixes tag). Fixes: 09a35126 ("phy: ti: tusb1210: Improve ulpi_read()/_write() error checking") Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Tested-by:
Ferry Toth <fntoth@gmail.com> Link: https://lore.kernel.org/r/20220613160848.82746-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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- 17 Jun, 2022 9 commits
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Lukas Bulwahn authored
Maintainers of the directory Documentation/devicetree/bindings/phy are also the maintainers of the corresponding directory include/dt-bindings/phy. Add the file entry for include/dt-bindings/phy to the appropriate section in MAINTAINERS. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613122621.18397-1-lukas.bulwahn@gmail.comSigned-off-by:
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Dmitry Baryshkov authored
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: da07a06b ("phy: qcom-qmp-pcie: drop support for non-PCIe PHY types") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220610185542.3662484-3-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: f575ac2d ("phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types") Signed-off-by:
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Roger Quadros authored
Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Reviewed-by:
Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20220526064121.27625-1-rogerq@kernel.orgSigned-off-by:
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Geert Uytterhoeven authored
Fix a misspelling of the word "functional". Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/3da9bd360e1c83007af0e0e90fa4e6c2b50fdab3.1652100633.git.geert+renesas@glider.beSigned-off-by:
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Alim Akhtar authored
Adds support for Tesla Full Self-Driving (FSD) ufs phy driver. This SoC has different cdr lock status offset. Signed-off-by:
Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by:
Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by:
Chanho Park <chanho61.park@samsung.com> Reviewed-by:
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Alim Akhtar authored
Move CDR lock offset to drv data so that it can be extended for other SoCs which are having CDR lock at different register offset. Signed-off-by:
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Alim Akhtar authored
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC. Signed-off-by:
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Douglas Anderson authored
We're supposed to list the supplies in the dt bindings but there are none in the eDP PHY bindings. Looking at the driver in Linux, I can see that there seem to be two relevant supplies: "vdda-phy" and "vdda-pll". Let's add those to the bindings. NOTE: from looking at the Qualcomm datasheet for sc7280, it's not immediately clear how to figure out how to fill in these supplies. The only two eDP related supplies are simply described as "power for eDP 0.9V circuits" and "power for eDP 1.2V circuits". From guessing and from comparing how a similar PHY is hooked up on other similar Qualcomm boards, I'll make the educated guess that the 1.2V supply goes to "vdda-phy" and the 0.9V supply goes to "vdda-pll" and I'll use that in the example here. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Sankeerth Billakanti <quic_sbillaka@quicinc.com> Link: https://lore.kernel.org/r/20220425140619.2.Iae013f0ff4599294189f3a6e91376fad137bbabf@changeidSigned-off-by:
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- 09 Jun, 2022 23 commits
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Dmitry Baryshkov authored
Switch qcom-qmp-usb driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-pcie-msm8996 driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-pcie driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-combo driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Each USB QMP PHY device provides just a single UFS PHY. Drop support for handling multiple child PHYs. Use phy->init_count to check if the PHY was initialized rather than duplicating this count. Acked-by:
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Dmitry Baryshkov authored
Each UFS QMP PHY device provides just a single UFS PHY. Drop support for handling multiple child PHYs. Acked-by:
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Dmitry Baryshkov authored
Each PCIe QMP PHY device provides just a single PCIe PHY. Drop support for handling multiple child PHYs. Acked-by:
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Dmitry Baryshkov authored
Remove the conditionals and options that are not used by any of USB PHY devices. Acked-by:
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Dmitry Baryshkov authored
Remove the conditionals and options that are not used by any of UFS PHY devices. Acked-by:
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Dmitry Baryshkov authored
Remove the conditionals and options that are not used by the MSM8996 PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is the case for this PHY. Acked-by:
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Dmitry Baryshkov authored
Remove the conditionals and options that are not used by any of PCIe PHY devices. Acked-by:
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Dmitry Baryshkov authored
Remove the conditionals and options that are not used by any of combo USB+DP PHY devices. Acked-by:
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Dmitry Baryshkov authored
Drop remaining support for PHY types other than USB. Acked-by:
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Dmitry Baryshkov authored
Drop remaining support for PHY types other than UFS. Acked-by:
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Dmitry Baryshkov authored
Drop remaining support for PHY types other than PCIe. Acked-by:
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Dmitry Baryshkov authored
Drop remaining support for PHY types other than PCIe. Acked-by:
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Dmitry Baryshkov authored
Drop remaining support for unused PHY types (PCIe, UFS). Acked-by:
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Dmitry Baryshkov authored
As we have switched to the new (split) QMP PHY driver, drop the old monolithic QMP driver source. Acked-by:
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Dmitry Baryshkov authored
Use new split QMP PHY driver and remove all monolith phy-qcom-qmp driver. Acked-by:
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Dmitry Baryshkov authored
Change all symbol names to start with qcom_qmp_phy_usb_ rather than old qcom_qmp_phy_ Acked-by:
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Dmitry Baryshkov authored
Change all symbol names to start with qcom_qmp_phy_ufs_ rather than old qcom_qmp_phy_ Acked-by:
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Dmitry Baryshkov authored
Change all symbol names to start with qcom_qmp_phy_pcie_msm8996_ rather than old qcom_qmp_phy_. Acked-by:
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Dmitry Baryshkov authored
Change all symbol names to start with qcom_qmp_phy_pcie_ rather than old qcom_qmp_phy_ Acked-by:
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