1. 29 Jun, 2017 24 commits
    • Maciej W. Rozycki's avatar
      MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn' · 7b82c105
      Maciej W. Rozycki authored
      Fix commit e50c0a8f ("Support the MIPS32 / MIPS64 DSP ASE.") and
      send SIGILL rather than SIGBUS whenever an unimplemented BPOSGE32 DSP
      ASE instruction has been encountered in `__compute_return_epc_for_insn'
      as our Reserved Instruction exception handler would in response to an
      attempt to actually execute the instruction.  Sending SIGBUS only makes
      sense for the unaligned PC case, since moved to `__compute_return_epc'.
      Adjust function documentation accordingly, correct formatting and use
      `pr_info' rather than `printk' as the other exit path already does.
      
      Fixes: e50c0a8f ("Support the MIPS32 / MIPS64 DSP ASE.")
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org # 2.6.14+
      Patchwork: https://patchwork.linux-mips.org/patch/16396/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      7b82c105
    • Maciej W. Rozycki's avatar
      MIPS: Fix unaligned PC interpretation in `compute_return_epc' · 11a3799d
      Maciej W. Rozycki authored
      Fix a regression introduced with commit fb6883e5 ("MIPS: microMIPS:
      Support handling of delay slots.") and defer to `__compute_return_epc'
      if the ISA bit is set in EPC with non-MIPS16, non-microMIPS hardware,
      which will then arrange for a SIGBUS due to an unaligned instruction
      reference.  Returning EPC here is never correct as the API defines this
      function's result to be either a negative error code on failure or one
      of 0 and BRANCH_LIKELY_TAKEN on success.
      
      Fixes: fb6883e5 ("MIPS: microMIPS: Support handling of delay slots.")
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org # 3.9+
      Patchwork: https://patchwork.linux-mips.org/patch/16395/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      11a3799d
    • Maciej W. Rozycki's avatar
      MIPS: Actually decode JALX in `__compute_return_epc_for_insn' · a9db101b
      Maciej W. Rozycki authored
      Complement commit fb6883e5 ("MIPS: microMIPS: Support handling of
      delay slots.") and actually decode the regular MIPS JALX major
      instruction opcode, the handling of which has been added with the said
      commit for EPC calculation in `__compute_return_epc_for_insn'.
      
      Fixes: fb6883e5 ("MIPS: microMIPS: Support handling of delay slots.")
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org # 3.9+
      Patchwork: https://patchwork.linux-mips.org/patch/16394/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a9db101b
    • Maciej W. Rozycki's avatar
      MIPS: math-emu: Prevent wrong ISA mode instruction emulation · 13769eba
      Maciej W. Rozycki authored
      Terminate FPU emulation immediately whenever an ISA mode switch has been
      observed.  This is so that we do not interpret machine code in the wrong
      mode, for example when a regular MIPS FPU instruction has been placed in
      a delay slot of a jump that switches into the MIPS16 mode, as with the
      following code (taken from a GCC test suite case):
      
      00400650 <set_fast_math>:
        400650:	3c020100 	lui	v0,0x100
        400654:	03e00008 	jr	ra
        400658:	44c2f800 	ctc1	v0,c1_fcsr
        40065c:	00000000 	nop
      
      [...]
      
      004012d0 <__libc_csu_init>:
        4012d0:	f000 6a02 	li	v0,2
        4012d4:	f150 0b1c 	la	v1,3f9430 <_DYNAMIC-0x6df0>
        4012d8:	f400 3240 	sll	v0,16
        4012dc:	e269      	addu	v0,v1
        4012de:	659a      	move	gp,v0
        4012e0:	f00c 64f6 	save	a0-a2,48,ra,s0-s1
        4012e4:	673c      	move	s1,gp
        4012e6:	f010 9978 	lw	v1,-32744(s1)
        4012ea:	d204      	sw	v0,16(sp)
        4012ec:	eb40      	jalr	v1
        4012ee:	653b      	move	t9,v1
        4012f0:	f010 997c 	lw	v1,-32740(s1)
        4012f4:	f030 9920 	lw	s1,-32736(s1)
        4012f8:	e32f      	subu	v1,s1
        4012fa:	326b      	sra	v0,v1,2
        4012fc:	d206      	sw	v0,24(sp)
        4012fe:	220c      	beqz	v0,401318 <__libc_csu_init+0x48>
        401300:	6800      	li	s0,0
        401302:	99e0      	lw	a3,0(s1)
        401304:	4801      	addiu	s0,1
        401306:	960e      	lw	a2,56(sp)
        401308:	4904      	addiu	s1,4
        40130a:	950d      	lw	a1,52(sp)
        40130c:	940c      	lw	a0,48(sp)
        40130e:	ef40      	jalr	a3
        401310:	653f      	move	t9,a3
        401312:	9206      	lw	v0,24(sp)
        401314:	ea0a      	cmp	v0,s0
        401316:	61f5      	btnez	401302 <__libc_csu_init+0x32>
        401318:	6476      	restore	48,ra,s0-s1
        40131a:	e8a0      	jrc	ra
      
      Here `set_fast_math' is called from `40130e' (`40130f' with the ISA bit)
      and emulation triggers for the CTC1 instruction.  As it is in a jump
      delay slot emulation continues from `401312' (`401313' with the ISA
      bit).  However we have no path to handle MIPS16 FPU code emulation,
      because there are no MIPS16 FPU instructions.  So the default emulation
      path is taken, interpreting a 32-bit word fetched by `get_user' from
      `401313' as a regular MIPS instruction, which is:
      
        401313:	f5ea0a92	sdc1	$f10,2706(t7)
      
      This makes the FPU emulator proceed with the supposed SDC1 instruction
      and consequently makes the program considered here terminate with
      SIGSEGV.
      
      A similar although less severe issue exists with pure-microMIPS
      processors in the case where similarly an FPU instruction is emulated in
      a delay slot of a register jump that (incorrectly) switches into the
      regular MIPS mode.  A subsequent instruction fetch from the jump's
      target is supposed to cause an Address Error exception, however instead
      we proceed with regular MIPS FPU emulation.
      
      For simplicity then, always terminate the emulation loop whenever a mode
      change is detected, denoted by an ISA mode bit flip.  As from commit
      377cb1b6 ("MIPS: Disable MIPS16/microMIPS crap for platforms not
      supporting these ASEs.") the result of `get_isa16_mode' can be hardcoded
      to 0, so we need to examine the ISA mode bit by hand.
      
      This complements commit 102cedc3 ("MIPS: microMIPS: Floating point
      support.") which added JALX decoding to FPU emulation.
      
      Fixes: 102cedc3 ("MIPS: microMIPS: Floating point support.")
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org # 3.9+
      Patchwork: https://patchwork.linux-mips.org/patch/16393/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      13769eba
    • Paul Burton's avatar
      MIPS: Use queued spinlocks (qspinlock) · 0b17c967
      Paul Burton authored
      This patch switches MIPS to make use of generically implemented queued
      spinlocks, rather than the ticket spinlocks used previously. This allows
      us to drop a whole load of inline assembly, share more generic code, and
      is also a performance win.
      
      Results from running the AIM7 short workload on a MIPS Creator Ci40 (ie.
      2 core 2 thread interAptiv CPU clocked at 546MHz) with v4.12-rc4
      pistachio_defconfig, with ftrace disabled due to a current bug, and both
      with & without use of queued rwlocks & spinlocks:
      
        Forks | v4.12-rc4 | +qlocks  | Change
       -------|-----------|----------|--------
           10 | 52630.32  | 53316.31 | +1.01%
           20 | 51777.80  | 52623.15 | +1.02%
           30 | 51645.92  | 52517.26 | +1.02%
           40 | 51634.88  | 52419.89 | +1.02%
           50 | 51506.75  | 52307.81 | +1.02%
           60 | 51500.74  | 52322.72 | +1.02%
           70 | 51434.81  | 52288.60 | +1.02%
           80 | 51423.22  | 52434.85 | +1.02%
           90 | 51428.65  | 52410.10 | +1.02%
      
      The kernels used for these tests also had my "MIPS: Hardcode cpu_has_*
      where known at compile time due to ISA" patch applied, which allows the
      kernel_uses_llsc checks in cmpxchg() & xchg() to be optimised away at
      compile time.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16358/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      0b17c967
    • Paul Burton's avatar
      MIPS: Use queued read/write locks (qrwlock) · 25da4e9d
      Paul Burton authored
      This patch switches MIPS to make use of generically implemented queued
      read/write locks, rather than the custom implementation used previously.
      This allows us to drop a whole load of inline assembly, share more
      generic code, and is also a performance win.
      
      Results from running the AIM7 short workload on a MIPS Creator Ci40 (ie.
      2 core 2 thread interAptiv CPU clocked at 546MHz) with v4.12-rc4
      pistachio_defconfig, with ftrace disabled due to a current bug, and both
      with & without use of queued rwlocks & spinlocks:
      
        Forks | v4.12-rc4 | +qlocks  | Change
       -------|-----------|----------|--------
           10 | 52630.32  | 53316.31 | +1.01%
           20 | 51777.80  | 52623.15 | +1.02%
           30 | 51645.92  | 52517.26 | +1.02%
           40 | 51634.88  | 52419.89 | +1.02%
           50 | 51506.75  | 52307.81 | +1.02%
           60 | 51500.74  | 52322.72 | +1.02%
           70 | 51434.81  | 52288.60 | +1.02%
           80 | 51423.22  | 52434.85 | +1.02%
           90 | 51428.65  | 52410.10 | +1.02%
      
      The kernels used for these tests also had my "MIPS: Hardcode cpu_has_*
      where known at compile time due to ISA" patch applied, which allows the
      kernel_uses_llsc checks in cmpxchg() & xchg() to be optimised away at
      compile time.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16357/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      25da4e9d
    • Paul Burton's avatar
      MIPS: cmpxchg: Rearrange __xchg() arguments to match xchg() · 4843cf8d
      Paul Burton authored
      The __xchg() function declares its first 2 arguments in reverse order
      compared to the xchg() macro, which is confusing & serves no purpose.
      Reorder the arguments such that __xchg() & xchg() match.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16356/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      4843cf8d
    • Paul Burton's avatar
      MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg() · 3ba7f44d
      Paul Burton authored
      Implement support for 1 & 2 byte cmpxchg() using read-modify-write atop
      a 4 byte cmpxchg(). This allows us to support these atomic operations
      despite the MIPS ISA only providing 4 & 8 byte atomic operations.
      
      This is required in order to support queued rwlocks (qrwlock) in a later
      patch, since these make use of a 1 byte cmpxchg() in their slow path.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16355/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      3ba7f44d
    • Paul Burton's avatar
      MIPS: cmpxchg: Implement 1 byte & 2 byte xchg() · b70eb300
      Paul Burton authored
      Implement 1 & 2 byte xchg() using read-modify-write atop a 4 byte
      cmpxchg(). This allows us to support these atomic operations despite the
      MIPS ISA only providing for 4 & 8 byte atomic operations.
      
      This is required in order to support queued spinlocks (qspinlock) in a
      later patch, since these make use of a 2 byte xchg() in their slow path.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16354/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b70eb300
    • Paul Burton's avatar
      MIPS: cmpxchg: Implement __cmpxchg() as a function · 8263db4d
      Paul Burton authored
      Replace the macro definition of __cmpxchg() with an inline function,
      which is easier to read & modify. The cmpxchg() & cmpxchg_local() macros
      are adjusted to call the new __cmpxchg() function.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16353/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8263db4d
    • Paul Burton's avatar
      MIPS: cmpxchg: Drop __xchg_u{32,64} functions · 62c6081d
      Paul Burton authored
      The __xchg_u32() & __xchg_u64() functions now add very little value.
      This patch therefore removes them, by:
      
        - Moving memory barriers out of them & into xchg(), which also removes
          the duplication & readies us to support xchg_relaxed() if we wish to.
      
        - Calling __xchg_asm() directly from __xchg().
      
        - Performing the check for CONFIG_64BIT being enabled in the size=8
          case of __xchg().
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16352/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      62c6081d
    • Paul Burton's avatar
      MIPS: cmpxchg: Error out on unsupported xchg() calls · d15dc68c
      Paul Burton authored
      xchg() has up until now simply returned the x parameter in cases where
      it is called with a pointer to a value of an unsupported size. This will
      often cause the calling code to hit a failure path, presuming that the
      value of x differs from the content of the memory pointed at by ptr, but
      we can do better by producing a compile-time or link-time error such
      that unsupported calls to xchg() are detectable earlier than runtime.
      
      This patch does this in the same was as is already done for cmpxchg(),
      using a call to a missing function annotated with __compiletime_error().
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16351/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      d15dc68c
    • Paul Burton's avatar
      MIPS: cmpxchg: Use __compiletime_error() for bad cmpxchg() pointers · 77299db8
      Paul Burton authored
      Our cmpxchg() implementation relies upon generating a call to a function
      which doesn't really exist (__cmpxchg_called_with_bad_pointer) to create
      a link failure in cases where cmpxchg() is called with a pointer to a
      value of an unsupported size.
      
      The __compiletime_error macro can be used to decorate a function such
      that a call to it generates a compile-time, rather than a link-time,
      error. This patch uses __compiletime_error to cause bad cmpxchg() calls
      to error out at compile time rather than link time, allowing errors to
      occur more quickly & making it easier to spot where the problem comes
      from.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16350/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      77299db8
    • Paul Burton's avatar
      MIPS: cmpxchg: Pull xchg() asm into a macro · 5154f3b4
      Paul Burton authored
      Use a macro to generate the 32 & 64 bit variants of the backing code for
      xchg(), much as is already done for cmpxchg(). This removes the
      duplication that could previously be found in __xchg_u32() &
      __xchg_u64().
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16349/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5154f3b4
    • Paul Burton's avatar
      MIPS: cmpxchg: Unify R10000_LLSC_WAR & non-R10000_LLSC_WAR cases · 6b1e7629
      Paul Burton authored
      Prior to this patch the xchg & cmpxchg functions have duplicated code
      which is for all intents & purposes identical apart from use of a
      branch-likely instruction in the R10000_LLSC_WAR case & a regular branch
      instruction in the non-R10000_LLSC_WAR case.
      
      This patch removes the duplication, declaring a __scbeqz macro to select
      the branch instruction suitable for use when checking the result of an
      sc instruction & making use of it to unify the 2 cases.
      
      In __xchg_u{32,64}() this means writing the branch in asm, where it was
      previously being done in C as a do...while loop for the
      non-R10000_LLSC_WAR case. As this is a single instruction, and adds
      consistency with the R10000_LLSC_WAR cases & the cmpxchg() code, this
      seems worthwhile.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16348/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6b1e7629
    • Miodrag Dinic's avatar
      MIPS: unaligned: Add DSP lwx & lhx missaligned access support · 3f88ec63
      Miodrag Dinic authored
      Add handling of missaligned access for DSP load instructions
      lwx & lhx.
      
      Since DSP instructions share SPECIAL3 opcode with other non-DSP
      instructions, necessary logic was inserted for distinguishing
      between instructions with SPECIAL3 opcode. For that purpose,
      the instruction format for DSP instructions is added to
      arch/mips/include/uapi/asm/inst.h.
      Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
      Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtech.com>
      Cc: James.Hogan@imgtec.com
      Cc: Paul.Burton@imgtec.com
      Cc: Raghu.Gandham@imgtec.com
      Cc: Leonid.Yegoshin@imgtec.com
      Cc: Douglas.Leung@imgtec.com
      Cc: Petar.Jovanovic@imgtec.com
      Cc: Goran.Ferenc@imgtec.com
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16511/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      3f88ec63
    • Leonid Yegoshin's avatar
      MIPS: R6: Fix PREF instruction usage by memcpy for MIPS R6 · 3daf281f
      Leonid Yegoshin authored
      Disable usage of PREF instruction usage by memcpy for MIPS R6.
      
      MIPS R6 redefines PREF instruction with smaller offset than
      ordinary MIPS. However, the memcpy code uses PREF instruction
      with offsets bigger than +-256 bytes.
      
      Malta kernels already disable usage of PREF for memcpy.
      
      This was found during adaptation of MIPS R6 for virtual board
      used by Android emulator.
      Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
      Signed-off-by: default avatarGoran Ferenc <goran.ferenc@imgtec.com>
      Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtech.com>
      Cc: James.Hogan@imgtec.com
      Cc: Paul.Burton@imgtec.com
      Cc: Raghu.Gandham@imgtec.com
      Cc: Leonid.Yegoshin@imgtec.com
      Cc: Douglas.Leung@imgtec.com
      Cc: Petar.Jovanovic@imgtec.com
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16510/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      3daf281f
    • Miodrag Dinic's avatar
      MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6 · 21855a6e
      Miodrag Dinic authored
      Add "-modd-spreg" when compiling the kernel for mips32r6 target.
      
      This makes sure the kernel builds properly even with toolchains that
      use "-mno-odd-spreg" by default. This is the case with Android gcc.
      Prior to this patch, kernel builds using gcc for Android failed with
      following error messages, if target architecture is set to mips32r6:
      
      arch/mips/kernel/r4k_switch.S: Assembler messages:
      .../r4k_switch.S:210: Error: float register should be even, was 1
      .../r4k_switch.S:212: Error: float register should be even, was 3
      .../r4k_switch.S:214: Error: float register should be even, was 5
      .../r4k_switch.S:216: Error: float register should be even, was 7
      .../r4k_switch.S:218: Error: float register should be even, was 9
      .../r4k_switch.S:220: Error: float register should be even, was 11
      .../r4k_switch.S:222: Error: float register should be even, was 13
      .../r4k_switch.S:224: Error: float register should be even, was 15
      .../r4k_switch.S:226: Error: float register should be even, was 17
      .../r4k_switch.S:228: Error: float register should be even, was 19
      .../r4k_switch.S:230: Error: float register should be even, was 21
      .../r4k_switch.S:232: Error: float register should be even, was 23
      .../r4k_switch.S:234: Error: float register should be even, was 25
      .../r4k_switch.S:236: Error: float register should be even, was 27
      .../r4k_switch.S:238: Error: float register should be even, was 29
      .../r4k_switch.S:240: Error: float register should be even, was 31
      make[2]: *** [arch/mips/kernel/r4k_switch.o] Error 1
      Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
      Signed-off-by: default avatarGoran Ferenc <goran.ferenc@imgtec.com>
      Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtec.com>
      Cc: James.Hogan@imgtec.com
      Cc: Paul.Burton@imgtec.com
      Cc: Raghu.Gandham@imgtec.com
      Cc: Leonid.Yegoshin@imgtec.com
      Cc: Douglas.Leung@imgtec.com
      Cc: Petar.Jovanovic@imgtec.com
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16509/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      21855a6e
    • Miodrag Dinic's avatar
      MIPS: cmdline: Add support for 'memmap' parameter · 296a7624
      Miodrag Dinic authored
      Implement support for parsing 'memmap' kernel command line parameter.
      
      This patch covers parsing of the following two formats for 'memmap'
      parameter values:
      
        - nn[KMG]@ss[KMG]
        - nn[KMG]$ss[KMG]
      
        ([KMG] = K M or G (kilo, mega, giga))
      
      These two allowed formats for parameter value are already documented
      in file kernel-parameters.txt in Documentation/admin-guide folder.
      Some architectures already support them, but Mips did not prior to
      this patch.
      
      Excerpt from Documentation/admin-guide/kernel-parameters.txt:
      
      memmap=nn[KMG]@ss[KMG]
          [KNL] Force usage of a specific region of memory.
          Region of memory to be used is from ss to ss+nn.
      
      memmap=nn[KMG]$ss[KMG]
          Mark specific memory as reserved.
          Region of memory to be reserved is from ss to ss+nn.
          Example: Exclude memory from 0x18690000-0x1869ffff
              memmap=64K$0x18690000
              or
              memmap=0x10000$0x18690000
      
      There is no need to update this documentation file with respect to
      this patch.
      Signed-off-by: default avatarMiodrag Dinic <miodrag.dinic@imgtec.com>
      Signed-off-by: default avatarGoran Ferenc <goran.ferenc@imgtec.com>
      Signed-off-by: default avatarAleksandar Markovic <aleksandar.markovic@imgtec.com>
      Cc: James.Hogan@imgtec.com
      Cc: Paul.Burton@imgtec.com
      Cc: Raghu.Gandham@imgtec.com
      Cc: Leonid.Yegoshin@imgtec.com
      Cc: Douglas.Leung@imgtec.com
      Cc: Petar.Jovanovic@imgtec.com
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16508/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      296a7624
    • Huacai Chen's avatar
      MIPS: Loogson: Make enum loongson_cpu_type more clear · b9c4dc2c
      Huacai Chen authored
      Sort enum loongson_cpu_type in a more reasonable manner, this makes the
      CPU names more clear and extensible. Those already defined enum values
      are renamed to Legacy_* for compatibility.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16591/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b9c4dc2c
    • Huacai Chen's avatar
      MIPS: Loongson-3: support irq_set_affinity() in i8259 chip · ecc38a09
      Huacai Chen authored
      With this patch we can set irq affinity via procfs, so as to improve
      network performance.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16590/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ecc38a09
    • Huacai Chen's avatar
      MIPS: Loongson-3: IRQ balancing for PCI devices · e1b88ca8
      Huacai Chen authored
      IRQ0 (HPET), IRQ1 (Keyboard), IRQ2 (Cascade), IRQ7 (SCI), IRQ8 (RTC)
      and IRQ12 (Mouse) are handled by core-0 locally. Other PCI IRQs (3, 4,
      5, 6, 14, 15) are balanced by all cores from Node-0. This can improve
      I/O performance significantly.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16589/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e1b88ca8
    • Huacai Chen's avatar
      MIPS: Loongson-3: Support 4 packages in CPU Hwmon driver · 99b0b5a3
      Huacai Chen authored
      Loongson-3 machines may have as many as 4 physical packages.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16588/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      99b0b5a3
    • Huacai Chen's avatar
      MIPS: Loongson: Add NMI handler support · b392ee07
      Huacai Chen authored
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: John Crispin <john@phrozen.org>
      Cc: Steven J . Hill <Steven.Hill@cavium.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16587/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b392ee07
  2. 28 Jun, 2017 16 commits