- 17 Jan, 2014 23 commits
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Tero Kristo authored
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by:
Tero Kristo <t-kristo@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Tero Kristo authored
This patch creates a unique node for each clock in the OMAP4 power, reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly different clock tree which is taken into account in the data. Signed-off-by:
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Tero Kristo authored
clk-43xx.c now contains the clock init functionality for am43xx, including DT clock registration and adding of static clkdev entries. Signed-off-by:
Nishanth Menon <nm@ti.com> Acked-by:
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Tero Kristo authored
clk-3xxx.c now contains the clock init functionality for omap3, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
OMAP3 has interface clocks in addition to functional clocks, which require special handling for the autoidle and idle status register offsets mainly. Signed-off-by:
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Tero Kristo authored
clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by:
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Tero Kristo authored
clk-7xx.c now contains the clock init functionality for dra7, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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J Keerthy authored
The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by:
J Keerthy <j-keerthy@ti.com> Signed-off-by:
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Roger Quadros authored
USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
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Tero Kristo authored
clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
clk-44xx.c now contains the clock init functionality for omap4, including DT clock registration and adding of static clkdev entries. Signed-off-by:
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Tero Kristo authored
ti,mux-clock provides now a binding for basic mux support. This is just using the basic clock type. Signed-off-by:
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Tero Kristo authored
Some OMAP clocks require knowledge about their parent clockdomain for book keeping purposes. This patch creates a new DT binding for TI clockdomains, which act as a collection of device clocks. Clockdomain itself is rather misleading name for the hardware functionality, as at least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either clocks and/or IP blocks, thus idle-domain or such might be more appropriate. For most cases on these SoCs, the kernel doesn't even need the information and the mappings can be ignored. Signed-off-by:
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Tero Kristo authored
This patch adds support for TI specific gate clocks. These behave as basic gate-clock, but have different ops / hw-ops for controlling the actual gate, for example waiting until the clock is ready. Several sub-types are supported: - ti,gate-clock: basic gate clock with default ops/hwops - ti,clkdm-gate-clock: clockdomain level gate control - ti,dss-gate-clock: gate clock with DSS specific hardware handling - ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling - ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling Signed-off-by:
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Tero Kristo authored
This behaves exactly in similar manner to basic fixed-factor-clock, but adds a few properties on top for handling clock hardware autoidling. Signed-off-by:
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Tero Kristo authored
This patch adds support for TI divider clock binding, which simply uses the basic clock divider to provide the features needed. Signed-off-by:
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Tero Kristo authored
This is a multipurpose clock node, which contains support for multiple sub-clocks. Uses basic composite clock type to implement the actual functionality, and TI specific gate, mux and divider clocks. Signed-off-by:
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Tero Kristo authored
TI clk driver now routes some of the basic clocks through own registration routine to allow autoidle support. This routine just checks a couple of device node properties and adds autoidle support if required, and just passes the registration forward to basic clocks. Signed-off-by:
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Tero Kristo authored
The OMAP clock driver now supports DPLL clock type. This patch also adds support for DT DPLL nodes. Signed-off-by:
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Tero Kristo authored
ti_dt_clk_init_provider() can now be used to initialize the contents of a single clock IP block. This parses all the clocks under the IP block and calls the corresponding init function for them. This patch also introduces a helper function for the TI clock drivers to get register info from DT and append the master IP info to this. Signed-off-by:
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Tero Kristo authored
Some devices require their clocks to be available with a specific dev-id con-id mapping. With DT, the clocks can be found by default only with their name, or alternatively through the device node of the consumer. With drivers, that don't support DT fully yet, add mechanism to register specific clock names. Signed-off-by:
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Tero Kristo authored
SOC_DRA7XX was under wrong menu within Kconfig file, which prevented DRA7XX only build. Fixed the kconfig options for this SoC as we are there. voltage.c needs to be added to the DRA7XX build also, otherwise DRA7XX only build will fail. Signed-off-by:
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Tero Kristo authored
DRA7XX and AM43XX were missing common clock code from the Makefile, which causes build breakage in DRA7XX / AM43XX only builds once clock support for these SoCs is added. Add the missing entries to the Makefile as preparation of this. Signed-off-by:
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- 16 Jan, 2014 16 commits
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Mike Turquette authored
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Stephen Boyd authored
Document the multimedia clock controller found on Qualcomm devices Cc: <devicetree@vger.kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
Document the global clock controller found on Qualcomm devices. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM8660 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the multimedia clock controller found on MSM 8960 based platforms. This should allow multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Add a driver for the global clock controller found on MSM8960 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by:
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Stephen Boyd authored
Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by:
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Stephen Boyd authored
Signed-off-by:
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Stephen Boyd authored
Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by:
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Stephen Boyd authored
Add support for Qualcomm's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed. Signed-off-by:
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Stephen Boyd authored
Add a clock type that associates a regmap pointer and some enable/disable bits with a clk_hw struct. This will be the struct that a hw specific implementation wraps if it wants to use the regmap helper functions. Signed-off-by:
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Stephen Boyd authored
Some of Qualcomm's clocks can change their parent and rate at the same time with a single register write. Add support for this hardware to the common clock framework by adding a new set_rate_and_parent() op. When the clock framework determines that both the parent and the rate are going to change during clk_set_rate() it will call the .set_rate_and_parent() op if available and fall back to calling .set_parent() followed by .set_rate() otherwise. Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Stephen Boyd authored
If a user of <linux/reset-controller.h> doesn't include <linux/of.h> before including reset-controller.h they'll get a warning as follows: include/linux/reset-controller.h:44:17: warning: 'struct of_phandle_args' declared inside parameter list This is because of_phandle_args is not forward declared. Add the declaration to silence this warning. Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Barry Song authored
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for prima2 and atlas6, there are many shared clocks but there are still some different register layout and hardware clocks, then result in different clock table. here we re-arch the driver to 1. clk-common.c provides common clocks for prima2 and atlas6, 2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides prima2 specific clocks and clock table. 3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides atlas6 specific clocks and clock table. 4. clk.h and clk.c expose external interfaces and provide uniform entry for both prima2 and atlas6. so both prima2 and atlas6 will get support by drivers/clk/sirf. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by:
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- 15 Jan, 2014 1 commit
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Mike Turquette authored
The composite clock's .determine_rate implementation can call the underyling .determine_rate callback corresponding to rate_hw or the underlying .determine_rate callback corresponding to mux_hw. In both cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into the correct callback. Reported-by:
Lemon Dai <dailemon.gl@gmail.com> Signed-off-by:
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