- 02 Nov, 2016 30 commits
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Rajendra Nayak authored
This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Rajendra Nayak authored
The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by:
Taniya Das <tdas@codeaurora.org> Signed-off-by:
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Rajendra Nayak authored
Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by:
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Rajendra Nayak authored
Add a function to do initial configuration of the alpha plls Signed-off-by:
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Rajendra Nayak authored
Some PLLs can support an HW FSM mode (different from the Votable FSMs, though its the same bit used to enable Votable FSMs as well as HW FSMs) which enables the HW to do the bypass/reset/enable-output-ctrl sequence on its own. So all thats needed from SW is to set the FSM_ENA bit. PLL_ACTIVE_FLAG is whats used to check if the PLL is active/enabled. Some of the PLLs which support HW FSM can also need an OFFLINE request that needs to be toggled across the enable/disable. We use a flag to identify such cases and handle them. Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: mmp: pxa910: fix return value check in pxa910_clk_init() clk: mmp: pxa168: fix return value check in pxa168_clk_init() clk: mmp: mmp2: fix return value check in mmp2_clk_init() clk: qoriq: Don't allow CPU clocks higher than starting value
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Abhishek Sahu authored
The current I2C freq table uses MND values which is not applicable for I2C since its RCG does not have MND counter. This patch updates the freq table for 19.05 MHz clk frequency with FEPLL_200 parent. Signed-off-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
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Robert Jarzmik authored
pxaxxx_get_clk_frequency_khz() needs several clocks to be available through clk_get(), ie. the cpu clocks, system bus clock and memory clocks. Add the missing clkdev so that their rate can be acquired. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Robert Jarzmik authored
The meaning of this bit was inverted : - when set to 0, system bus clock is half of the CPU run clock - when set to 1, system bus clock is the CPU run clock Signed-off-by:
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Robert Jarzmik authored
The t bit of clkfcfg doesn't affect the core pll clock, but it makes core clock select between core pll clock and core run clock. As such remove it from the core pll rate reporting function, while it remains in clk_pxa27x_core_get_parent(). Signed-off-by:
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Robert Jarzmik authored
This is a cleanup patch to remove unused values not used in their respective functions. Signed-off-by:
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Mingkai Hu authored
Signed-off-by:
Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by:
Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by:
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Axel Lin authored
Drop the assignment of regmap_read return code to val, so the code checks the value read. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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Wei Yongjun authored
Fix the retrn value check which testing the wrong variable in pxa910_clk_init(). Fixes: 2bc61da9 ("clk: mmp: add pxa910 DT support for clock driver") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Wei Yongjun authored
Fix the retrn value check which testing the wrong variable in pxa168_clk_init(). Fixes: ab08aefc ("clk: mmp: add pxa168 DT support for clock driver") Signed-off-by:
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Wei Yongjun authored
Fix the retrn value check which testing the wrong variable in mmp2_clk_init(). Fixes: 1ec770d9 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by:
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Julia Lawall authored
Adjust variables to correspond to the names used in the parameter list of the function. Move the struct device * variable up to the place where it appears in the parameter list. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
Adjust the documentation to use the actual function names. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by:
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Marcin Wojtas authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by:
Marcin Wojtas <mw@semihalf.com> Signed-off-by:
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Krzysztof Kozlowski authored
s2mps11 and max77686 clock drivers can be compile tested to increase build coverage. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Geert Uytterhoeven authored
The intention was to enable the checks if debugging is enabled, not disabled. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Arvind Yadav authored
Free memory mapping, if lpc18xx_ccu_init() is not successful. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Vladimir Zapolskiy authored
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that 1) a divider clock may be set to zero value, 2) divider's zero value is interpreted as a non-divided clock. On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated. The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Reviewed-by:
Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by:
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Scott Wood authored
The boot-time frequency of a CPU is considered its rated maximum, as we have no other source of such information. However, this was previously only used for chips with 80% restrictions on secondary PLLs. This usually wasn't a problem because most chips/configs boot with a divider of /1, with other dividers being used only for dynamic frequency reduction. However, at least one config (LS1021A at less than 1 GHz) uses a different divider for top speed. This was causing cpufreq to set a frequency beyond the chip's rated speed. This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs, similar to the existing 80% limit that only applied to some. Signed-off-by:
Scott Wood <oss@buserror.net> Cc: stable@vger.kernel.org Signed-off-by:
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Rajendra Nayak authored
Add gpu gdsc data for msm8996 Signed-off-by:
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Rajendra Nayak authored
Add a flag to mark gdscs which need to support the clamp deassert/assert before and after the gdsc enable/disable Signed-off-by:
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Emil Lundmark authored
The audio and video PLLs are designed to have a precision of 1 Hz if some conditions are met. The current implementation only allows a precision that depends on the rate of the parent clock. E.g., if the parent clock is 24 MHz, the precision will be 24 Hz; or more generally the precision will be p / 10^6 Hz where p is the parent clock rate. This comes down to how the register values for the PLL's fractional loop divider are chosen. The clock rate calculation for the PLL is PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM) or with a shorter notation r = p * (d + a / b) In addition to all variables being integers, we also have the following conditions: 27 <= d <= 54 -2^29 <= a <= 2^29-1 0 < b <= 2^30-1 |a| < b Here, d, a and b are register values for the fractional loop divider. We want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate function. Currently, d and b are chosen as d = r / p b = 10^6 hence we get the poor precision. And a is defined in terms of r, d, p and b: a = (r - d * p) * b / p I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as b = p We can do this since |a| < b |(r - d * p) * b / p| < b |r - d * p| < p Which have two solutions, one of them is when p < 0, so we can skip that one. The other is when p > 0 and p * (d - 1) < r < p * (d + 1) Substitute d = r / p: (r - p) < r < (r + p) <=> p > 0 So, as long as p > 0, we can chose b = p. This is a good choise for b since a = (r - d * p) * b / p = (r - d * p) * p / p = r - d * p r = p * (d + a / b) = p * d + p * a / b = p * d + p * a / p = p * d + a and if d = r / p: a = r - d * p = r - r / p * p = 0 r = p * d + a = p * d + 0 = p * r / p = r I reckon this is the intention by the design of the clock rate formula. Signed-off-by:Emil Lundmark <emil@limesaudio.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: imx: fix integer overflow in AV PLL round rate clk: xgene: Don't call __pa on ioremaped address clk: rockchip: don't return NULL when failing to register ddrclk branch
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Stephen Boyd authored
Merge tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Fix return value in error case of new ddrclk type. * tag 'v4.9-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: don't return NULL when failing to register ddrclk branch
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Emil Lundmark authored
Since 'parent_rate * mfn' may overflow 32 bits, the result should be stored using 64 bits. The problem was discovered when trying to set the rate of the audio PLL (pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but the actual rate returned was 192.000570 MHz. The round rate function should have been able to return 196.608 MHz, i.e., the desired rate. Fixes: ba7f4f55 ("clk: imx: correct AV PLL rate formula") Cc: Anson Huang <b20788@freescale.com> Signed-off-by:
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- 28 Oct, 2016 6 commits
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Laura Abbott authored
ioremaped addresses are not linearly mapped so the physical address can not be figured out via __pa. More generally, there is no guarantee that backing value of an ioremapped address is a physical address at all. The value here is only used for debugging so just drop the call to __pa on the ioremapped address. Fixes: 6ae5fd38 ("clk: xgene: Silence sparse warnings") Signed-off-by:
Laura Abbott <labbott@redhat.com> Acked-by:
Loc Ho <lho@apm.com> Signed-off-by:
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Gabriel Fernandez authored
This patch adds the QSPI clock for stm32f469 discovery board. The gate mapping is a little bit different from stm32f429 soc. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Gabriel Fernandez authored
This patch introduces the support of the RTC clock. RTC clock can have 3 sources: lsi, lse and hse_rtc. Signed-off-by:
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Gabriel Fernandez authored
This patch introduces the support of the LSI & LSE clocks. The clock drivers needs to disable the power domain write protection using syscon/regmap to enable these clocks. Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT
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Marek Szyprowski authored
The Exynos PMU node is an interrupt, clock and PMU (Power Management Unit) controller, and these functionalities are supported by different drivers that matches the same compatible strings. Since commit 989eafd0 ("clk: core: Avoid double initialization of clocks") the OF core flags clock controllers registered with the CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same compatible string will not be registered. This prevents the PMU platform device to be created, so the Exynos PMU driver is never probed. This breaks (among other things) Suspend-to-RAM. Fix this by changing CLKOUT driver initialization method to CLK_OF_DECLARE_DRIVER(), which doesn't clear the OF_POPULATED flag, so later a platform device is created and the Exynos PMU platform driver can be be probed properly. Fixes: 989eafd0 ("clk: core: Avoid double initialization of clocks") Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
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- 23 Oct, 2016 4 commits
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Michael Turquette authored
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Neil Armstrong authored
Add OX820 bindings and remove clock indices from bindings since they are present in the dt-bindings headers files. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Acked-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-7-narmstrong@baylibre.com
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Neil Armstrong authored
Add support for the Oxford Semiconductor OX820 SoC gate clocks along the OX810SE SoC support. This rework on concerns the gate clocks since they are different. Future PLL handling code will be added for OX820. Signed-off-by:
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Neil Armstrong authored
Make usage of static tables identified by the OF match table to feed devm_clk_hw_register() and use of_clk_add_hw_provider(). This structure is cleaner and simplifies adding new SoC support while having common probe and gate ops code. Signed-off-by:
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