- 19 Feb, 2016 9 commits
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Sergei Shtylyov authored
Define the generic R8A7794 part of the EtherAVB device node. Based on the commit 46ece349 ("ARM: shmobile: r8a7791: add EtherAVB DT support"). Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Sergei Shtylyov authored
Add the EtherAVB clock to the R8A7794 device tree. Based on the commit eaa870b3 ("ARM: shmobile: r8a7791: add EtherAVB clock"). Signed-off-by:
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Simon Horman authored
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication. Changelog text from a similar patch by Sudeep Holla. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Sudeep Holla <sudeep.holla@arm.com>
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Geert Uytterhoeven authored
Add a device node for the L2 cache, and link the CPU nodes to it. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the L2 cache, and link the CPU node to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the L2 cache, and link the CPU nodes to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by:
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Geert Uytterhoeven authored
Add device nodes for the L2 caches, and link the CPU nodes to them. The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways). The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by:
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Geert Uytterhoeven authored
Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways), and located in PM domain A3SM. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways), and located in PM domain A3KM. Signed-off-by:
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Kuninori Morimoto authored
This patch enables to use thermal-zone on r8a7793. This thermal sensor can measure temperature from -40000 to 125000, but over 117000 can be critical on this chip. Thus, default critical temperature is now set as 115000 (this driver is using 5000 steps) (Current critical temperature is using it as 90000, but there is no big reason about it) And it doesn't check thermal zone periodically (same as current behavior). You can exchange it by modifying polling-delay[-passive] property. You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS, but you need to take care to use it, since it will call orderly_poweroff() it it reaches to the value. echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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- 16 Feb, 2016 2 commits
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Kuninori Morimoto authored
This patch enables to use thermal-zone on r8a7791. This thermal sensor can measure temperature from -40000 to 125000, but over 117000 can be critical on this chip. Thus, default critical temperature is now set as 115000 (this driver is using 5000 steps) (Current critical temperature is using it as 90000, but there is no big reason about it) And it doesn't check thermal zone periodically (same as current behavior). You can exchange it by modifying polling-delay[-passive] property. You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS, but you need to take care to use it, since it will call orderly_poweroff() it it reaches to the value. echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp Signed-off-by:
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Kuninori Morimoto authored
This patch enables to use thermal-zone on r8a7790. This thermal sensor can measure temperature from -40000 to 125000, but over 117000 can be critical on this chip. Thus, default critical temperature is now set as 115000 (this driver is using 5000 steps) (Current critical temperature is using it as 90000, but there is no big reason about it) And it doesn't check thermal zone periodically (same as current behavior). You can exchange it by modifying polling-delay[-passive] property. You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS, but you need to take care to use it, since it will call orderly_poweroff() it it reaches to the value. echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp Signed-off-by:
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- 15 Feb, 2016 6 commits
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Sergei Shtylyov authored
When finishing the Porter sound support patch, I managed to call the JP3 jumper SW3 in the comment. Fix this along with (also miscalled) jumper positions... Fixes: 493b4da7 ("ARM: dts: porter: add sound support") Signed-off-by:
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Simon Horman authored
Use recently added fallback compatibility string in r8a7794 device tree. Signed-off-by: -
Simon Horman authored
Use recently added fallback compatibility string in r8a7791 device tree. Signed-off-by: -
Simon Horman authored
Use recently added fallback compatibility string in r8a7790 device tree. Signed-off-by: -
Simon Horman authored
Use recently added fallback compatibility string in r8a7791 device tree. Signed-off-by: -
Simon Horman authored
Use recently added fallback compatibility string in r8a7790 device tree. Signed-off-by:
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- 09 Feb, 2016 23 commits
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates: - SCIF: - Supports now 50, 75, 110, 1152000, 1500000, 2000000, and 4000000 bps, - Perfect match for standard 50-460800, and 9216000 bps. - More accurate 576000 bps. - HSCIF: - Supports now 50, 75, 110, 134, 150, and 200 bps, - Perfect match for standard 50-460800, and 9216000 bps. - More accurate 576000, 1152000, 3000000, 3500000, and 4000000 bps. Signed-off-by:Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. This increases the range and accuracy of supported baud rates. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF and HSCIF device nodes. This increases the range and accuracy of supported baud rates on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
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