- 23 Jun, 2024 4 commits
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Taniya Das authored
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Taniya Das authored
Update the GDSC wait_val fields as per the default hardware values as otherwise they would lead to GDSC FSM state to be stuck and causing failures to power on/off. Also add the GDSC flags as applicable and add support to control PCIE GDSC's using collapse vote registers. Fixes: 08c51ceb ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by:
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Taniya Das authored
The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by:
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Taniya Das authored
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes: 160758b0 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.comSigned-off-by:
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- 21 Jun, 2024 3 commits
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Luo Jie authored
The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/Signed-off-by:
Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.comSigned-off-by:
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Lukas Bulwahn authored
Commit 8cab0336 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@redhat.com> Fixes: 8cab0336 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by:
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Elliot Berman authored
This symbol is selected by a couple drivers, but isn't used by anyone and hasn't been for years now. Drop it. No functional change intended. Signed-off-by:
Elliot Berman <quic_eberman@quicinc.com> Reviewed-by:
Mike Tipton <quic_mdtipton@quicinc.com> Reviewed-by:
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- 13 Jun, 2024 24 commits
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Konrad Dybcio authored
Add a driver for the GPU clock controller block found on the QCM2290 SoC. Reviewed-by:
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Konrad Dybcio authored
Commit 134b55b7 ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by:
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Bjorn Andersson authored
Merge the QCM2290 GPUCC binding through a topic branch to allow for it to also be merged into the DeviceTree branch.
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Konrad Dybcio authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Luo Jie authored
The clock controller driver of qca8386/qca8084 is registered as the MDIO device, the hardware register is accessed by MDIO bus that is normally used to access general PHY device, which is different from the current existed qcom clock controller drivers using ioremap to access hardware clock registers, nsscc-qca8k is accessed via an MDIO bus. MDIO bus is commonly utilized by both qca8386/qca8084 and other PHY devices, so the mutex lock mdio_bus->mdio_lock should be used instead of using the mutex lock of remap. To access the hardware clock registers of qca8386/qca8084, there is a special MDIO frame sequence, which needs to be sent to the device. Enable the reference clock before resetting the clock controller, the reference clock rate is fixed to 50MHZ. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Luo Jie authored
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Tested-by:
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Luo Jie authored
QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Luo Jie authored
Add the clk_branch2_prepare_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin lock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_prepare_ops is used. Acked-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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Krzysztof Kozlowski authored
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by:
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- 31 May, 2024 6 commits
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Dmitry Baryshkov authored
Add schema for the Global Clock Controller (GCC) present on the Qualcomm MDM9615 platform. Signed-off-by:
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Dmitry Baryshkov authored
On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Move requirement for the '#power-domain-cells' out of the common qcom,gcc.yaml into individual schema files. For the platforms that do not provide power-domains, explicitly forbid having the '#power-domain-cells' property. Suggested-by:
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Dmitry Baryshkov authored
The only platform remaining in qcom,gcc-other.yaml is MDM9607. Drop the stale mentioning of gcc-msm8953.h include and rename the schema file accordingly. Signed-off-by:
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Taniya Das authored
Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 1daec8cf ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Signed-off-by:
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Taniya Das authored
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. When retention bit of the clock is set the memories of the subsystem will retain the logic across power states. Fixes: a3cc0921 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by:
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Taniya Das authored
Add support to update the GDSC transition delay values to avoid the GDSC FSM state stuck issues without which it could lead to GDSC power on/off failures. Signed-off-by:
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- 28 May, 2024 2 commits
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Alexandru Gagniuc authored
The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel. Signed-off-by:
Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by:
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Alexandru Gagniuc authored
Add defines for the missing PCIe PIPE clocks. Signed-off-by:
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- 27 May, 2024 1 commit
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Danila Tikhonov authored
Add support for the video clock controller found on SM7150. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240505201038.276047-9-danila@jiaxyga.comSigned-off-by:
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