Add a DTS file for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
sub-board (RTP8A779G0ASKB0SE0SA000), and include it from the main
r8a779g0-white-hawk.dts.

For now its contents are limited to the Board ID EEPROM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/991600919513dd05a9a7d9c170c6924baf14d1a2.1662715538.git.geert+renesas@glider.be

Add a DTS file for the R-Car V4H White Hawk CSI/DSI sub-board
(RTP8A779G0ASKB0SC0SA000), and include it from the main
r8a779g0-white-hawk.dts.

For now its contents are limited to the Board ID EEPROM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/265f7782743c539c57906e8207785f8b0d80d5d0.1662715538.git.geert+renesas@glider.be

Enable the I2C0 bus on the White Hawk CPU board, and describe the I2C
EEPROMs present on the White Hawk CPU and BreakOut boards.

Based on a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d01cada6f2d3e44dd6cb26cfa8e4ce6382f1fbff.1662715538.git.geert+renesas@glider.be

Add device nodes for the I2C Bus Interfaces on the Renesas R-Car V4H
(R8A779G0) SoC.

Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/272fd18fed2d7addfbdb7945ae2134988a7c3a7e.1662715538.git.geert+renesas@glider.be

Complete the description of the serial console and the external serial
clock by adding pin control.

Based on larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/74c862ef6e46b4af398d9b371ff38fae17b3db05.1662715538.git.geert+renesas@glider.be

Add a device node for the Pin Function Controller on the Renesas R-Car
V4H (R8A779G0) SoC.

Based on a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ecddcadd2fad46b1cf4c9be3ec750f360b9730e4.1662715538.git.geert+renesas@glider.be

Enable the watchdog timer on the White Hawk CPU board.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/77a0e29d965032115de1f07ceecb2d5d07db74eb.1662715538.git.geert+renesas@glider.be

Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas
R-Car V4H (R8A779G0) SoC.

Based on a patch in the BSP by Thanh Quan.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/187904c279be6654ea3deb11b7250b64dd18c3b5.1662715538.git.geert+renesas@glider.be

The CN10/CN11 on RZ/N1-EB board are headers to add jumpers to select which
CAN interface to route to the real CAN connector J16.

For a normal use case either we need to wire CAN1 or CAN2, but not both.

This patch enables CAN1 and disables CAN2 by default assuming CN10/CN11
is wired for CAN1.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220902062752.56841-1-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220830164518.1381632-3-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

There is not much point in having separate entries for the ARM/Renesas
ARM64 and ARM/SH-Mobile ARM architectures, as they have the same
maintainers, use the same development collaboration infrastructure, and
share many files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a869b8afdc47aa637ebeefcc1ca7bc61244f34b9.1660898008.git.geert+renesas@glider.be

Renesas fixes for v6.0

  - Fix the serial console on the Renesas White Hawk development board.

This patch adds r8a77980A V3H2 (= r8a77980 ES2) Condor-I board
basic support.
Signed-off-by: Andrey Dolnikov <andrey.dolnikov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87y1v64nko.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

This patch adds r8a77980A V3H2 (= r8a77980 ES2) basic SoC
support. It is using r8a77980 (= V3H) setting as-is for now.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87zgfm4nkw.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

We have V3H Condor board, and will have V3H2 Condor-I board.
This patch adds condor-common.dtsi to share the common settings
between these boards.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qsy625m.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

With 'unevaluatedProperties' support implemented, there are a number of
warnings when running dtbs_check:

arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb: spi@ee200000: Unevaluated properties are not allowed ('clock-names' was unexpected)
	From schema: Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml

The main problem is that the DT bindings do not allow clock-names.
So just drop the clock-names properties from the SoC DTSI files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220829215128.5983-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add MSIOF nodes for R-Car S4-8.
Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
[thanh: added DMA]
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
[wsa: removed mso clock from clocks-property]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220829124130.2412-1-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-7-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

As RZ/G2 SoCs do not support DVFS, the "iic-dvfs" module was renamed to
"iic-pmic" in the RZ/G Series, 2nd Generation User’s Manual: Hardware
Rev. 1.00.

See also commit a636d803 ("arm64: dts: renesas: rzg2: Rename
i2c_dvfs to iic_pmic"), which apparently forgot to update RZ/G2H.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7d60653d4d63904dc025a133297a53eb885fa064.1661525361.git.geert+renesas@glider.be

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-6-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-5-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-4-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-3-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I2C aliases are not a property of a SoC. They belong to board files
where they are named accordingly in the schematics.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220825071022.7864-2-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220819193944.337599-4-phil.edworthy@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add device nodes for the I2C controllers that are not assigned to the
ISP.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220819193944.337599-3-phil.edworthy@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

The interrupt number for the HSCIF0 serial port, which serves as the
serial console on the White Hawk board, is incorrect, causing userspace
to hang immediately as soon as it tries to print something.
Kernel output is unaffected, as it is printed using polling.

Fixes: 987da486 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/751dcef40d4534e856ed49b1d5b3a3e8d365ec42.1661419377.git.geert+renesas@glider.be

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220804190846.128370-1-phil.edworthy@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: cf40c968 ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: 7c2b8198 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-2-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: f9a2adcc ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes")
Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Replace the clk node names audio-clk{1,2} with audio{1,2}-clk as per
the device tree specification.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220729084527.388023-1-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add DMA properties to RSPI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220728122312.189766-4-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add DMA properties to RSPI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220728122312.189766-3-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add DMA properties to RSPI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220728122312.189766-2-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-3-wsa+renesas@sang-engineering.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
and ETH1 respectively.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on
RZ/G2L (and alike) SoC's so that these can be used in the first cell of
interrupt specifiers.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220722151155.21100-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Add support for the Renesas R-Car H3Ne-1.7G (R8A779MB) SoC, which is a
different grading of the R-Car H3-N (R8A77951) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/862a5eecc850cbb90af86a56513b644b638fb62b.1656072871.git.geert+renesas@glider.be

Add required properties in pinctrl node to handle GPIO interrupts.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220718195651.7711-5-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>