- 06 Jul, 2022 1 commit
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Kuogee Hsieh authored
This patch add regulator_set_load() before enable regulator at eDP phy driver. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1657038556-2231-2-git-send-email-quic_khsieh@quicinc.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 05 Jul, 2022 24 commits
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Neil Armstrong authored
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY used to communicate with DSI panels. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220705075650.3165348-3-narmstrong@baylibre.comSigned-off-by:
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Neil Armstrong authored
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI panels, this adds the bindings. This Analog D-PHY works with a separate Digital MIPI D-PHY. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220705075650.3165348-2-narmstrong@baylibre.comSigned-off-by:
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Jiang Jian authored
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/broadcom/phy-brcm-usb-init.c line: 864 * Make sure the the second and third memory controller changed to * Make sure the second and third memory controller Signed-off-by:
Jiang Jian <jiangjian@cdjrlc.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220621122401.115500-1-jiangjian@cdjrlc.comSigned-off-by:
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Peter Geis authored
The initial otg state for the phy defaults to device mode. The actual state isn't detected until an ID IRQ fires. Fix this by syncing the ID state during initialization. Fixes: 51a9b2c0 ("phy: rockchip-inno-usb2: Handle ID IRQ") Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Reviewed-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.comSigned-off-by:
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Robert Marko authored
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, so add the support for the Gen3 one. It uses the same register layout as IPQ6018. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Robert Marko authored
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, document the bindings for the Gen3 one. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-2-robimarko@gmail.comSigned-off-by:
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Robert Marko authored
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by:
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Johan Hovold authored
Use lower case hex consistently for define values. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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Johan Hovold authored
Clean up the QMP defines by removing some stray white space and making sure values are aligned. Signed-off-by:
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Johan Hovold authored
Clean up the QMP v4 and v5 defines by moving a few entries that were out of order. Signed-off-by:
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Johan Hovold authored
Clean up the pipe clock handling by using dev_err_probe() to handle probe deferral and dropping the obsolete comment that claimed that the pipe clock was optional for some other PHY types. Signed-off-by:
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Johan Hovold authored
Drop the obsolete pipe clock handling which was used to treat the pipe clock as optional for types other than PCIe and USB and which is no longer needed since splitting the PHY driver. Signed-off-by:
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Johan Hovold authored
Drop the obsolete pipe clock handling which was used to treat the pipe clock as optional for types other than PCIe and USB and which is no longer needed since splitting the PHY driver. Signed-off-by:
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Markus Schneider-Pargmann authored
This is a new driver that supports the integrated DisplayPort phy for mediatek SoCs, especially the mt8195. The phy is integrated into the DisplayPort controller and will be created by the mtk-dp driver. This driver expects a struct regmap to be able to work on the same registers as the DisplayPort controller. It sets the device data to be the struct phy so that the DisplayPort controller can easily work with it. The driver does not have any devicetree bindings because the datasheet does not list the controller and the phy as distinct units. The interaction with the controller can be covered by the configure callback of the phy framework and its displayport parameters. Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by:
Guillaume Ranquet <granquet@baylibre.com> [Bo-Chen: Modify reviewers' comments.] Signed-off-by:
Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220624062725.4095-1-rex-bc.chen@mediatek.comSigned-off-by:
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Rahul T R authored
Add support new compatible for dphy-tx on j721e and implement dphy ops required. Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Reviewed-by:
Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220623125433.18467-4-r-ravikumar@ti.comSigned-off-by:
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Rahul T R authored
Add support for band ctrl config for dphy tx. Signed-off-by:
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Rahul T R authored
Add compatible to support dphy tx on j721e Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
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Peter Geis authored
If a phy supply is designated but isn't available at probe time, an EPROBE_DEFER is returned. Use dev_err_probe to prevent this from incorrectly printing during boot. Signed-off-by:
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Jiang Jian authored
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c line: 139 * when in RxULPS check state, after the the logic enable the analog, changed to * when in RxULPS check state, after the logic enable the analog, Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
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Vidya Sagar authored
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by:
Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20220629060435.25297-9-vidyas@nvidia.comSigned-off-by:
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Vidya Sagar authored
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by:
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Jianjun Wang authored
Add PCIe GEN3 PHY driver support on MediaTek chipsets. Signed-off-by:
Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
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Jianjun Wang authored
Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
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Andy Shevchenko authored
On some platforms, like Intel Merrifield, the writing values during power on may timeout: tusb1210 dwc3.0.auto.ulpi: error -110 writing val 0x41 to reg 0x80 phy phy-dwc3.0.auto.ulpi.0: phy poweron failed --> -110 dwc3 dwc3.0.auto: error -ETIMEDOUT: failed to initialize core dwc3: probe of dwc3.0.auto failed with error -110 which effectively fails the probe of the USB controller. Drop the check as it was before the culprit commit (see Fixes tag). Fixes: 09a35126 ("phy: ti: tusb1210: Improve ulpi_read()/_write() error checking") Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Hans de Goede <hdegoede@redhat.com> Tested-by:
Ferry Toth <fntoth@gmail.com> Link: https://lore.kernel.org/r/20220613160848.82746-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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- 17 Jun, 2022 9 commits
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Lukas Bulwahn authored
Maintainers of the directory Documentation/devicetree/bindings/phy are also the maintainers of the corresponding directory include/dt-bindings/phy. Add the file entry for include/dt-bindings/phy to the appropriate section in MAINTAINERS. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613122621.18397-1-lukas.bulwahn@gmail.comSigned-off-by:
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Dmitry Baryshkov authored
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: da07a06b ("phy: qcom-qmp-pcie: drop support for non-PCIe PHY types") Signed-off-by:
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Dmitry Baryshkov authored
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: f575ac2d ("phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types") Signed-off-by:
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Roger Quadros authored
Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Reviewed-by:
Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20220526064121.27625-1-rogerq@kernel.orgSigned-off-by:
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Geert Uytterhoeven authored
Fix a misspelling of the word "functional". Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/3da9bd360e1c83007af0e0e90fa4e6c2b50fdab3.1652100633.git.geert+renesas@glider.beSigned-off-by:
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Alim Akhtar authored
Adds support for Tesla Full Self-Driving (FSD) ufs phy driver. This SoC has different cdr lock status offset. Signed-off-by:
Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by:
Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by:
Chanho Park <chanho61.park@samsung.com> Reviewed-by:
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Alim Akhtar authored
Move CDR lock offset to drv data so that it can be extended for other SoCs which are having CDR lock at different register offset. Signed-off-by:
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Alim Akhtar authored
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC. Signed-off-by:
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Douglas Anderson authored
We're supposed to list the supplies in the dt bindings but there are none in the eDP PHY bindings. Looking at the driver in Linux, I can see that there seem to be two relevant supplies: "vdda-phy" and "vdda-pll". Let's add those to the bindings. NOTE: from looking at the Qualcomm datasheet for sc7280, it's not immediately clear how to figure out how to fill in these supplies. The only two eDP related supplies are simply described as "power for eDP 0.9V circuits" and "power for eDP 1.2V circuits". From guessing and from comparing how a similar PHY is hooked up on other similar Qualcomm boards, I'll make the educated guess that the 1.2V supply goes to "vdda-phy" and the 0.9V supply goes to "vdda-pll" and I'll use that in the example here. Signed-off-by:
Sankeerth Billakanti <quic_sbillaka@quicinc.com> Link: https://lore.kernel.org/r/20220425140619.2.Iae013f0ff4599294189f3a6e91376fad137bbabf@changeidSigned-off-by:
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- 09 Jun, 2022 6 commits
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Dmitry Baryshkov authored
Switch qcom-qmp-usb driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-pcie-msm8996 driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-pcie driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Switch qcom-qmp-combo driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by:
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Dmitry Baryshkov authored
Each USB QMP PHY device provides just a single UFS PHY. Drop support for handling multiple child PHYs. Use phy->init_count to check if the PHY was initialized rather than duplicating this count. Acked-by:
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Dmitry Baryshkov authored
Each UFS QMP PHY device provides just a single UFS PHY. Drop support for handling multiple child PHYs. Acked-by:
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