- 12 Apr, 2017 21 commits
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git://github.com/BayLibre/clk-mesonMichael Turquette authored
Pull AmLogic clk driver updates from Jerome Brunet: 2nd Amlogic clock driver update for 4.12: * Protect against holes in onecell_data * Fix divison by zero and overflow in the mpll driver * Add audio clock divider driver for i2s clocks * Add i2s and spdif master clocks
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Michael Turquette authored
Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next Same great taste as the previous pull request, but now with 50% less DT bikeshedding! Amlogic clock driver updates for v4.12 - meson8: add some new PLLs - new clocks for Mali - misc fixes.
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Peter De Schrijver authored
In case there are multiple notify chains for the same clocks (because they were registered by different users), we need to propagate potential failure of any single one of them to the caller. Otherwise we eg risk violating the V/f curve when a notifier is used for DVFS. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Peter De Schrijver authored
For validation purposes, it's often useful to be able to retrieve the list of possible parents in userspace. Add a debugfs file for every clock which has more than 1 possible parent. Signed-off-by:
Jon Mayo <jmayo@nvidia.com> [sboyd@codeaurora.org: Remove useless cast from void and extra newline] Signed-off-by:
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Robin van der Gracht authored
Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Robin van der Gracht <robin@protonic.nl> Signed-off-by:
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Stephen Boyd authored
These should be const. Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Jun Nie <jun.nie@linaro.org> Signed-off-by:
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Shawn Guo authored
It adds zx296718 pll_vga clock for VGA support, so that VGA device can get required pixel rate from clock driver for different display mode. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Reviewed-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
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Shawn Guo authored
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of of postdiv2 field. The consequence is that functions like hw_to_idx() and zx_pll_enable() will end up tampering the postdiv2 of the PLL. Let's fix it by defining pd_bit 0xff which is obviously invalid for a bit position and having PLL driver check the validity before operating on the bit. Signed-off-by:
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Shawn Guo authored
To support VOU VGA display driver with different modes, we need to set flag for a few clocks, so that clk_set_rate() call in VOU driver can get VGA device desired pixel rate. While at it, the divider between pll_vga and clk_vga gets corrected, as it's 1:1 instead of 1:2. Signed-off-by:
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Robin van der Gracht authored
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register. Reviewed-by:
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Michael Turquette authored
Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull Tegra clk driver updates from Thierry Reding: This contains a bunch of fixes and cleanups, mostly to the Tegra210 clock driver. * tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) clk: tegra: Don't reset PLL-CX if it is already enabled clk: tegra: Add missing Tegra210 clocks clk: tegra: Propagate clk_out_x rate to parent clk: tegra: Fix build warnings on Tegra20/Tegra30 clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on clk: tegra: Add SATA seq input control clk: tegra: Add Tegra210 special resets clk: tegra: Rework pll_u clk: tegra: Implement reset control reset clk: tegra: Fix disable unused for clocks sharing enable bit clk: tegra: Handle UTMIPLL IDDQ clk: tegra: Add aclk clk: tegra: Add super clock mux/divider clk: tegra: Define Tegra210 DMIC clocks clk: tegra: Fix constness for peripheral clocks clk: tegra: Define Tegra210 DMIC sync clocks clk: tegra: Add CEC clock clk: tegra: Fix type for m field clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: Don't warn for PLL defaults unnecessarily ...
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Kuninori Morimoto authored
Thus CS2000 datasheet is indicating below, this patch follows it. WARNING: All "Reserved" registers must maintain their default state to ensure proper functional operation. Signed-off-by:Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Rajendra Nayak authored
Fix a typo which caused both vfe0 and vfe1 powerdomains to be named as vfe0. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Fixes: 7e824d50 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by:
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Gabriel Fernandez authored
Use a classic polling to test bit ready. And the shift of the bit ready of LSE & LSI were wrongs. Fixes: 861adc44 ("clk: stm32f4: Add LSI & LSE clocks") Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
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Ray Jui authored
Remove the redundant check of 'rate' in the if statement of the 'pll_set_rate' function Reported-by:
David Binderman <dcb314@hotmail.com> Signed-off-by:
Ray Jui <ray.jui@broadcom.com> Fixes: 5fe225c1 ("clk: iproc: add initial common clock support") Signed-off-by:
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Michael Turquette authored
Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: General rockchip clock changes for 4.12. Contains some new clock-ids as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add pll_wait_lock for pll_enable clk: rockchip: rename RK1108 to RV1108 dt-bindings: rk1108-cru: rename RK1108 to RV1108 clk: rockchip: mark some rk3368 core-clks as critical clk: rockchip: export SCLK_TIMERXX id for timers on rk3368 clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs clk: rockchip: fix up rk3368 timer-ids clk: rockchip: add rk3328 clk_mac2io_ext ID clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
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Michael Turquette authored
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the Clock Pulse Generator / Module Standby and Software Reset module on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in some areas. - Add IMR clocks for R-Car H3 and M3-W, - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0, - Small fixes and cleanups. * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions clk: renesas: cpg-mssr: Add support for fixing up clock tables clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() clk: renesas: r8a7796: Reformat core clock table clk: renesas: r8a7795: Reformat core clock table clk: renesas: r8a7796: Correct name of watchdog clock clk: renesas: r8a7795: Correct name of watchdog clock clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs clk: renesas: r8a7796: Add IMR clocks clk: renesas: r8a7795: Add IMR clocks
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Stephen Boyd authored
* clk-fixes: clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
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Gabriel Fernandez authored
0000: PLLQ = 0, wrong configuration 0001: PLLQ = 1, wrong configuration ... 0010: PLLQ = 2 0011: PLLQ = 3 0100: PLLQ = 4 ... 1111: PLLQ = 1 Use divider table to exclude 0 and 1 values. Fixes: 83135ad3 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards") Signed-off-by:
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https://github.com/t-kristo/linux-pmStephen Boyd authored
* 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm: clk: ti: convert to use proper register definition for all accesses clk: ti: dpll44xx: fix clksel register initialization clk: ti: gate: export gate_clk_ops locally clk: ti: divider: add driver internal API for parsing divider data clk: ti: divider: convert TI divider clock to use its own data representation clk: ti: mux: convert TI mux clock to use its internal data representation clk: ti: drop unnecessary MEMMAP_ADDRESSING flag clk: ti: omap4: cleanup unnecessary clock aliases clk: ti: enforce const types on string arrays clk: ti: move omap2_init_clk_clkdm under TI clock driver clk: ti: add clkdm_lookup to the exported functions clk: ti: use automatic clock alias generation framework clk: ti: add API for creating aliases automatically for simple clock types clk: ti: add support for automatic clock alias generation clk: ti: remove un-used definitions from public clk_hw_omap struct
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Leo Yan authored
The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 07 Apr, 2017 8 commits
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Martin Blumenstingl authored
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz. Multiplying this with SDM_DEN results in a value greater than 32bits. This is not a problem on the 64bit Meson GX SoCs, but it may result in undefined behavior on the older 32bit Meson8b SoC. While rate_from_params was only introduced recently to make the math reusable from _round_rate and _recalc_rate the original bug exists much longer. Fixes: 1c50da4f ("clk: meson: add mpll support") Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> [as discussed on the ml, use DIV_ROUND_UP_ULL] Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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Martin Blumenstingl authored
According to the public datasheet all register bits in HHI_MPLL_CNTL7, HHI_MPLL_CNTL8 and HHI_MPLL_CNTL9 default to zero. On all GX SoCs these seem to be initialized by the bootloader to some default value. However, on my Meson8 board they are not initialized, leading to a division by zero in rate_from_params as the math is: (parent_rate * SDM_DEN) / ((SDM_DEN * 0) + 0) According to the datasheet, the minimum n2 value is 4. The rate provided by the clock when n2 is less than this minimum is unpredictable. In such case, we report an error. Although the rate_from_params function was only introduced recently the original bug has been there for much longer. It was only exposed recently when the MPLL clocks were added to the Meson8b clock driver. Fixes: 1c50da4f ("clk: meson: add mpll support") Reviewed-by:
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Jerome Brunet authored
This adds the cts_i958 clock to control the clock source of the spdif output block. This mux is not explicitly mentionned in the documentation but it is critical to the spdif dai. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer) Acked-by:
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Jerome Brunet authored
Add the spdif master clock also referred as cts_mclk_i958 Acked-by:
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Jerome Brunet authored
Add the i2s master clock also referred as cts_amclk Acked-by:
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Jerome Brunet authored
The audio divider needs a specific clock divider driver. With am mpll parent clock, which is able to provide a fairly precise rate, the generic divider tends to select low value of the divider. In such case the quality of the clock is very poor. For the same final rate, maximizing the audio clock divider value and selecting the corresponding mpll rate gives better results. This is what this driver aims to acheive. So far, so good. Cc: Hendrik v. Raven <hendrik@consetetur.de> Acked-by:
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Jerome Brunet authored
The clock controller is getting more complex and it might be possible, in the future, to have holes in the clk_hw_onecell_data array. Just make sure we skip those holes if it ever happens. Acked-by:
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Jerome Brunet authored
Suggested-by:
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- 04 Apr, 2017 11 commits
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Kevin Hilman authored
* v4.12/clk-drivers: clk: meson-gxbb: Add GXL/GXM GP0 Variant clk: meson-gxbb: Add GP0 PLL init parameters clk: meson: Add support for parameters for specific PLLs clk: meson-gxbb: Add MALI clocks clk: meson: mpll: correct N2 maximum value clk: meson8b: add the mplls clocks 0, 1 and 2 clk: meson: gxbb: mpll: use rw operation clk: meson: mpll: add rw operation clk: gxbb: put dividers and muxes in tables clk: meson8b: put dividers and muxes in tables clk: meson: add missing const qualifiers on gate arrays clk: meson: fix SET_PARM macro
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Neil Armstrong authored
The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM SoCs embeds a different GP0 PLL, and needs different parameters with a vendor provided reduced rate table. This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order to use the GXL GP0 PLL instead of the GXBB specific one. Signed-off-by:
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Neil Armstrong authored
Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be initializated in the the GP0 control registers before configuring the rate with the rate table provided parameters. GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure. Signed-off-by:
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Neil Armstrong authored
In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific parameters in order to initialize and lock correctly. This patch adds an optional PARAM table used to initialize the PLL to a default value with it's parameters in order to achieve to desired frequency. The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization steps, and these are exposed along the PARAM table. Signed-off-by:
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Neil Armstrong authored
The Mali is clocked by two identical clock paths behind a glitch free mux to safely change frequency while running. The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. Expose these two clocks trees using generic clocks. Finally the glitch free mux is added as "mali" clock. Signed-off-by:
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Neil Armstrong authored
Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Neil Armstrong authored
This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by:
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Neil Armstrong authored
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by:
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Jerome Brunet authored
Signed-off-by:
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Jon Hunter authored
Commit 8dce89a1 ("clk: tegra: Don't warn for PLL defaults unnecessarily") changed the tegra210_pllcx_set_defaults() function causing the PLL to always be reset regardless of whether it is in-use. This function was changed so that resetting of the PLL will only be skipped if the PLL is enabled AND 'pllcx->params->defaults_set' is not true. However, the 'pllcx->params->defaults_set' is always true and hence, the PLL is now always reset. This causes the boot to fail on the Tegra210 Smaug where the PLL is already enabled and in-use. Fix this by only resetting the PLL if not in-use and only printing the warning that the defaults are not set after we have checked the default settings. Fixes: 8dce89a1 ("clk: tegra: Don't warn for PLL defaults unnecessarily") Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-By:
Thierry Reding <treding@nvidia.com>
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Peter De Schrijver authored
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210. Signed-off-by:
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