- 12 Aug, 2019 36 commits
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Le Ma authored
Init MC_MGCG/LS flag. Also apply to athub CG. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Add 2 mmhub instances CG Signed-off-by:
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Le Ma authored
Follow the hw spec, and no need to consider gfxoff on Arcturus Signed-off-by:
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Le Ma authored
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before drm/amdgpu: enable gfx clock gating for Arcturus Signed-off-by: -
Tao Zhou authored
feature mask info is enough for rocm tool, "cat /sys/class/drm/card0/device/ras/features" will get the info like this: feature mask: 0x3ffb Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Kenneth Feng authored
change the smu_read_sensor sequence to: asic specific sensor read -> smu v11 specific sensor read -> smu v11 common sensor read Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Le Ma authored
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Le Ma authored
Init sdma MGCG/LS flag Signed-off-by:
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Le Ma authored
Add ARCTURUS case in sdma set clockgating function Signed-off-by:
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Le Ma authored
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part. Signed-off-by:
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Le Ma authored
Init hdp MGCG/LS flag as Vega20 Signed-off-by:
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Le Ma authored
Add hdp CGLS for Arcturus in set common clockgating function Signed-off-by:
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Le Ma authored
Init gfx MGCG/LS and CGCG/LS flag. Signed-off-by:
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Le Ma authored
Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus. Signed-off-by:
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Tao Zhou authored
enable mmhub ras feature and create sysfs/debugfs node for mmhub Signed-off-by:
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Tao Zhou authored
call mmhub ras query/inject in amdgpu ras Signed-off-by:
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Tao Zhou authored
add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by:
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Tao Zhou authored
ras sub block index could be passed from shell command Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Guchun Chen authored
Sub_block_index can be passed from user level, so add one check before accessing the array first to prevent array index out of bound problem. Signed-off-by:
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tiancyin authored
update the smu11_driver_if_navi10.h since navi14 smu fw update to 53.12 Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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tiancyin authored
[why] navi14 share same defination of smu interface version with navi10, anyone of them update the version may break the other one's version checking. [how] create different version defination, so that they can update their version separately. Reviewed-by:
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Alex Deucher authored
Add the navi14 PCI device id. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Michel Dänzer authored
DC already handles this correctly since amdgpu minor version 31. Bump the minor version again so that xf86-video-amdgpu can take advantage of this working without DC as well now. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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David Francis authored
This file was accidentally added to the driver during Navi promotion Nothing includes it. No makefile attempts to compile it, and it would fail compilation if they tried Remove it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>w Signed-off-by:
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Xiaojie Yuan authored
enables vcn medium grained clock gating Signed-off-by:
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Xiaojie Yuan authored
enables athub medium grained clock gating and memory light sleep Signed-off-by:
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Xiaojie Yuan authored
add navi12 define Signed-off-by:
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Xiaojie Yuan authored
enables ih clock gating Signed-off-by:
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Xiaojie Yuan authored
enables mmhub medium grained clock gating and memory light sleep Signed-off-by:
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Xiaojie Yuan authored
add navi12 define Signed-off-by:
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Xiaojie Yuan authored
enables sdma medium grained clock gating and memory light sleep Signed-off-by:
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Xiaojie Yuan authored
add navi12 define Signed-off-by:
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Xiaojie Yuan authored
enables hdp medium grained clock gating and memory light sleep Signed-off-by:
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Xiaojie Yuan authored
enables following gfx clock gating features: - medium grained clock gating - medium grained light sleep - coarse grained clock gating - cp memory light sleep - rlc memory light sleep CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it. Signed-off-by:
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Marek Olšák authored
This reverts commit 9ed2c993. SET_CONFIG_REG writes to memory if register shadowing is enabled, causing a VM fault. NGG streamout is unstable anyway, so all UMDs should use legacy streamout. I think Mesa is the only driver using NGG streamout. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
drm-next-5.4-2019-08-09: Same as drm-next-5.4-2019-08-06, but with the readq/writeq stuff fixed and 5.3-rc3 backmerged. amdgpu: - Add navi14 support - Add navi12 support - Add Arcturus support - Enable mclk DPM for Navi - Misc DC display fixes - Add perfmon support for DF - Add scatter/gather display support for Raven - Improve SMU handling for GPU reset - RAS support for GFX - Drop last of drmP.h - Add support for wiping memory on buffer release - Allow cursor async updates for fb swaps - Misc fixes and cleanups amdkfd: - Add navi14 support - Add navi12 support - Add Arcturus support - CWSR trap handlers updates for gfx9, 10 - Drop last of drmP.h - Update MAINTAINERS radeon: - Misc fixes and cleanups - Make kexec more reliable by tearing down the GPU ttm: - Add release_notify callback uapi: - Add wipe memory on release flag for buffer creation Signed-off-by:
Dave Airlie <airlied@redhat.com> [airlied: resolved conflicts with ttm resv moving] From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190809184807.3381-1-alexander.deucher@amd.com
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- 09 Aug, 2019 4 commits
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Alex Deucher authored
Linux 5.3-rc3 Signed-off-by: -
Tao Zhou authored
atomic 64 bits REG operations are useless currently Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Tao Zhou authored
implement 64 bits operations via 32 bits interface v2: make use of lower_32_bits() and upper_32_bits() macros Reviewed-by:
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Tao Zhou authored
what we really want is a read or write that is guaranteed to be 64 bits at a time, atomic64 operations are supported on all architectures Signed-off-by:
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