- 15 Dec, 2022 26 commits
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Tao Zhou authored
Send handling request to host. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tao Zhou authored
Send message to host and host will handle it. v2: split the patch into two parts, one is for mxgpu ai and another one is for common poison consumption handler. Signed-off-by:
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Alvin Lee authored
[Description] - Current policy does not support HDMI VRR by default, so we cannot enable FPO / SubVP (DRR) cases Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: -Fix array index out of bound error -Speed up DML fast vadlaite -Implement multiple secure display -MST HDCP for multiple display -Add DPIA notification -Add support for three new square pattern variant Reviewed-by:
Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Fangzhi Zuo authored
[Why && How] On dcn32, HW supports odm transition in fast update. Hence this error message is considered false positive. Downgrade the error level to avoid catching unnecessary attention. Reviewed-by:
Dillon Varone <Dillon.Varone@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] DP2.1 specs has brought 3 new variants of sqaure patterns with different pre-shoot and de-emphasis equalization requirements. The commit adds logic to identify these variants and apply corresponding eqaulization requirements into hardware lane settings. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY] Subvp portion validation currently assumes that if vlevel provided does not support pstate, then none will, and so subvp is not used. [HOW] After get vlevel, use lowest vlevel that supports pstate if it exists, and use that for subvp validation. Reviewed-by:
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Samson Tam authored
[Why] When we have a PSR display, we will not be requesting data from memory anymore. So we report back true for no memory request case. [How] Check for PSR by checking PSR version in link settings Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - When merging a pipe that was previously pipe split, we need to also clear the link resources or the next stream/plane that uses the pipe may have an incorrect link resource state Reviewed-by:
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Mustapha Ghaddar authored
[WHY] Adding the new DPIA NOTIFY packets from DMUB As per the design with Cruise to account for 250ms response delay otherwise [HOW] Added th DPIA NOTIFY logic as per DMUB logic Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Roman Li authored
[Why] In case of failure to resume MST topology after suspend, an emtpty mst tree prevents further mst hub detection on the same connector. That causes the issue with MST hub hotplug after it's been unplug in suspend. [How] Stop topology manager on the connector after detecting DM_MST failure. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] in dc_link_dp there still exist a few places where we call dio encoders without checking current enabled encoder type. The change is to make these places to call hwss equivalent functions so it won't mistakenly program a wrong type encoder. Reviewed-by:
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Leo (Hanghong) Ma authored
Workaround no longer needed. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Roman Li authored
[Why] Fixing smatch error: dm_resume() error: we previously assumed 'aconnector->dc_link' could be null [How] Check if dc_link null at the beginning of the loop, so further checks can be dropped. Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Ian Chen authored
[WHY] It causes regression AMD source will not write DPCD 340. Reviewed-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - FW scheduling algorithm doesn't take into account of it's a center timing - This affects where the subvp mclk switch can be scheduled (prevents HUBP vline interrupt from coming in if scheduled incorrectly) - Block subvp center timing cases for now Reviewed-by:
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Dillon Varone authored
[Description] Modify soc BB to reduce expected sdp bandwidth and align with measurements to fix underflow issues. Reviewed-by:
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Dillon Varone authored
[Description] Add debug bit to disable unbounded requesting. Reviewed-by:
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Ilya Bakoulin authored
[Why] Iterating over every voltage state when we need to validate thousands of configurations all at once (i.e. display hotplug) can take a significant amount of time. [How] Check just the highest voltage state when fast_validate is true to verify whether the configuration can work at all, then do a proper validation including all voltage states later when fast_validate is false. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by:
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Alan Liu authored
[Why] Fix problems when we disable secure_display. [How] - Reset secure display context after disabled - A secure_display_context is dedicate to a crtc, so we set the crtc for it when we create the context. Reviewed-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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Charlene Liu authored
This reverts commit c800d9ff. [why] revert for now because this change exposed other issue. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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Alan Liu authored
[Why] Current secure display only work with single display, now make it work with multiple displays. [How] Create secure_display_context for each crtc instance to store its own Region of Interest (ROI) information. v2: squash in warning fix (Alex) Reviewed-by:
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Evan Quan authored
Update the reported maximum shader clock to the value which can be guarded to be achieved on all cards. This is to align with Window setting. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Correct the pstate standard/peak profiling mode clock settings for SMU13.0.0. Signed-off-by:
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Evan Quan authored
To better support UMD pstate profilings, the GPO feature needs to be switched on/off accordingly. Signed-off-by:
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Evan Quan authored
To better support UMD pstate profilings, the GPO feature needs to be switched on/off accordingly. Signed-off-by:
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- 14 Dec, 2022 14 commits
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Christian König authored
This reverts commit f9d00a4a. This causes problem for KFD because when we overcommit we accidentially bind the BO to GTT for moving it into VRAM. We also need to make sure that this is done only as fallback after trying to evict first. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Luben Tuikov authored
Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this function takes an "offset" argument which is the offset off of VRAM, and as such allocation always takes place in VRAM. Thus, the "domain" argument is unnecessary. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Luben Tuikov authored
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the requested memory exists, else we get a kernel oops when dereferencing "man". v2: Make the patch standalone, i.e. not dependent on local patches. v3: Preserve old behaviour and just check that the manager pointer is not NULL. v4: Complain if GTT domain requested and it is uninitialized--most likely a bug. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Signed-off-by: -
Luben Tuikov authored
Always check if fru_addr is not NULL. This commit also fixes a "smatch" warning. v2: Add a Fixes tag. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Dan Carpenter <error27@gmail.com> Cc: kernel test robot <lkp@intel.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Fixes: afbe5d1e ("drm/amdgpu: Bug-fix: Reading I2C FRU data on newer ASICs") Signed-off-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Christian König authored
Instead of reserving a VMID for a single process allow that many processes use the reserved ID. This allows for proper isolation between the processes. Signed-off-by:
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Christian König authored
This is completely pointless since the VMID always stays allocated until the VM is idle. Signed-off-by:
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Christian König authored
This should probably not access job->vm and also emit the SPM switch under the conditional execute. Signed-off-by:
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Christian König authored
Bas pointed out that this isn't working as expected and could cause crashes. Fix the handling by storing the marker that a switch is needed inside the job instead. Reported-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Evan Quan authored
Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with correct data. Signed-off-by:
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Evan Quan authored
Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with correct data. Signed-off-by:
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Felix Kuehling authored
Add a per-process MMU notifier lock for processing notifiers from userptrs. Use that lock to properly synchronize page table updates with MMU notifiers. Signed-off-by:
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Yifan Zhang authored
Add display SG support for DCN 3.1.4. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Christian König authored
When buffers are freed during suspend there is no guarantee that they can be re-allocated during resume. The PSP subsystem seems to be quite buggy regarding this, so add a WARN_ON() to point out those bugs. Signed-off-by:
Alex Deucher <alexdeucher@amd.com> Tested-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Christian König authored
We not only need to make sure that we have a BO, but also that the BO has some backing store. Fixes: d1a372af ("drm/amdgpu: Set MTYPE in PTE based on BO flags") Signed-off-by:
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