1. 11 Nov, 2019 4 commits
    • Tudor Ambarus's avatar
      mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 · bb2dc7f4
      Tudor Ambarus authored
      JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20,
      refers to this bit as "bit 1 of the status register 2".
      Rename the macro accordingly.
      Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
      bb2dc7f4
    • Tudor Ambarus's avatar
      mtd: spi-nor: Extend the SR Read Back test · 4da11da1
      Tudor Ambarus authored
      Test that all the bits from Status Register 1 and Status Register 2
      were written correctly.
      Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
      4da11da1
    • Tudor Ambarus's avatar
      mtd: spi-nor: Rework the disabling of block write protection · 3e0930f1
      Tudor Ambarus authored
      spi_nor_unlock() unlocks blocks of memory or the entire flash memory
      array, if requested. clear_sr_bp() unlocks the entire flash memory
      array at boot time. This calls for some unification, clear_sr_bp() is
      just an optimization for the case when the unlock request covers the
      entire flash size.
      
      Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is
      just a call to spi_nor_unlock() for the entire flash memory array.
      This fixes a bug that was present in spi_nor_spansion_clear_sr_bp().
      When the QE bit was zero, we used the Write Status (01h) command with
      one data byte, which might cleared the Status Register 2. We now always
      use the Write Status (01h) command with two data bytes when
      SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2.
      
      The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't
      support the CR Read command, we make an assumption about the value of
      the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then
      spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can
      be sure the QE bit has value one, because of the previous call to
      spi_nor_quad_enable().
      
      Get rid of the MFR handling and implement specific manufacturer
      default_init() fixup hooks.
      
      Note that this changes a bit the logic for the SNOR_MFR_ATMEL,
      SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel,
      Intel and SST chips did not set the locking ops, but unlocked the entire
      flash at boot time, while now they are setting the locking ops to
      stm_locking_ops. This should work, since the disable of the block
      protection at the boot time used the same Status Register bits to unlock
      the flash, as in the stm_locking_ops case.
      Suggested-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
      Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
      3e0930f1
    • Tudor Ambarus's avatar
      mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() · 39d1e334
      Tudor Ambarus authored
      Make sure that when doing a lock() or an unlock() operation we don't clear
      the QE bit from Status Register 2.
      
      JESD216 revB or later offers information about the *default* Status
      Register commands to use (see BFPT DWORDS[15], bits 22:20). In this
      standard, Status Register 1 refers to the first data byte transferred on a
      Read Status (05h) or Write Status (01h) command. Status register 2 refers
      to the byte read using instruction 35h. Status register 2 is the second
      byte transferred in a Write Status (01h) command.
      
      Industry naming and definitions of these Status Registers may differ.
      The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20.
      There are cases in which writing only one byte to the Status Register 1
      has the side-effect of clearing Status Register 2 and implicitly the Quad
      Enable bit. This side-effect is hit just by the
      BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases.
      Suggested-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
      Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
      39d1e334
  2. 07 Nov, 2019 12 commits
  3. 02 Nov, 2019 4 commits
  4. 01 Nov, 2019 12 commits
  5. 23 Oct, 2019 6 commits
  6. 20 Oct, 2019 2 commits