- 11 Nov, 2019 4 commits
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Tudor Ambarus authored
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Test that all the bits from Status Register 1 and Status Register 2 were written correctly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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- 07 Nov, 2019 12 commits
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Tudor Ambarus authored
Demystify where the EIO error occurs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Check that all the bits written in the write_sr_and_check() method match the status_new received value. Failing to write the other bits is dangerous too, extend the check. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
When the Read-Modify-Write-Read-Back Quad Enable methods failed on the Read-Back, they returned -EINVAL. Since this is an I/O error, return -EIO. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Merge static int spi_nor_write_sr(struct spi_nor *nor, u8 val) static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) into static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) The Status Register can be written with one or two bytes. Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case of errors. The callers didn't check their return value, make them of type void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Rename 'sst_write_err' label to 'out' as it is no longer generic for all the errors in the sst_write() method, and may introduce confusion. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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Tudor Ambarus authored
What most users care about is "my dev is not working properly". All low level information should be discovered when activating the debug traces. Keep error messages just for the following cases: - when the SR/FSR report program or erase fails, or attempts of modifying a protected sector, - when the JEDEC ID is not recognized, - when the resume() call fails, - when the spi_nor_check() fails. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
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- 02 Nov, 2019 4 commits
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Sergei Shtylyov authored
spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Sergei Shtylyov authored
spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e12 ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Mika Westerberg authored
Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Tudor Ambarus authored
Print identifying information about struct device. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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- 01 Nov, 2019 12 commits
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Tudor Ambarus authored
Constify the data to write to the Status Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
In case the write of the first byte failed, retlen was incorrectly incremented to *retlen += actual; on the exit path. retlen should be incremented when actual data was written to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Let the callers pass the pointer to the DMA-able buffer where the value of the Flag Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Caller stops compare the return value of spi_nor_read_fsr() with negative, spi_nor_read_fsr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
ret is already of type int. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
spi_mem_exec_op() nor->controller_ops->write_reg() nor->controller_ops->read_reg() spi_nor_wait_till_ready() Return 0 on success, -errno otherwise. Stop compare with negative and compare with zero in all the register operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Group all register methods up in the file, to avoid forward declarations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Two new lines, one after another, drop one. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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- 23 Oct, 2019 6 commits
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Tudor Ambarus authored
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', to comply with the SPI NOR int (*read_reg)() method. The 'const' qualifier has no meaning for parameters passed by value, drop it. Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, drop it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
Move all SPI NOR controller driver specific ops in a dedicated structure. 'struct spi_nor' becomes lighter. Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'. Rename wite/read_buf to buf, the name of the functions are suggestive enough. Constify buf in int (*write_reg). Comply with these changes in the SPI NOR controller drivers. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Tudor Ambarus authored
The pointer to 'struct spi_nor' is kzalloc'ed above in the code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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DENG Qingfang authored
Tested on HiWiFi C526A Datasheet is available at: http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdfSigned-off-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Jethro Beekman authored
Now that SPI flash controllers without a software sequencer are supported, it's trivial to add support for CNL and its PCI ID. Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdfSigned-off-by: Jethro Beekman <jethro@fortanix.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Jethro Beekman authored
Some flash controllers don't have a software sequencer. Avoid configuring the register addresses for it, and double check everywhere that its not accidentally trying to be used. Every use of `sregs` is now guarded by a check of `sregs` or `swseq_reg`. The check might be done in the calling function. Signed-off-by: Jethro Beekman <jethro@fortanix.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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- 20 Oct, 2019 2 commits
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Linus Torvalds authored
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Linus Torvalds authored
Merge tag 'kbuild-fixes-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull more Kbuild fixes from Masahiro Yamada: - fix a bashism of setlocalversion - do not use the too new --sort option of tar * tag 'kbuild-fixes-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: kheaders: substituting --sort in archive creation scripts: setlocalversion: fix a bashism kbuild: update comment about KBUILD_ALLDIRS
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