- 21 Aug, 2013 1 commit
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Scott Wood authored
Some CPUs (such as e500v1/v2) don't implement mftb and will take a trap. mfspr should work on everything that has a timebase, and is the preferred instruction according to ISA v2.06. Currently we get away with mftb on 85xx because the assembler converts it to mfspr due to -Wa,-me500. However, that flag has other effects that are undesireable for certain targets (e.g. lwsync is converted to sync), and is hostile to multiplatform kernels. Thus we would like to stop setting it for all e500-family builds. mftb/mftbu instances which are in 85xx code or common code are converted. Instances which will never run on 85xx are left alone. Signed-off-by:Scott Wood <scottwood@freescale.com>
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- 20 Aug, 2013 1 commit
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Scott Wood authored
Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject to a similar race condition as doing mftbu/mftbl on 32-bit. The lower half of timebase is updated before the upper half; thus, we can share the workaround for a similar bug on Cell. This workaround involves looping if the lower half of timebase is zero, thus avoiding the need for a scratch register (other than CR0). This workaround must be avoided when the timebase is frozen, such as during the timebase sync code. This deals with kernel and vdso accesses, but other userspace accesses will of course need to be fixed elsewhere. Signed-off-by:
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- 16 Aug, 2013 1 commit
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Benjamin Herrenschmidt authored
When reworking udbg_16550.c I forgot to remove the old and now useless code for the CONFIG_PPC_EARLY_DEBUG_WSP case, which doesn't build as a result. I also missed a cast. Signed-off-by:Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 14 Aug, 2013 37 commits
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Anton Blanchard authored
Our ppc64 spinlocks and rwlocks use a trick where a lock token and the paca index are placed in the lock with a single store. Since we are using two u16s they need adjusting for little endian. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Anton Blanchard authored
We need to set ELF_DATA correctly on LE coredumps. Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
Add little endian support for demuxing SMP IPIs Signed-off-by:
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Anton Blanchard authored
Alistair noticed we got a SIGILL on userspace mfpvr instructions. Remove the little endian check in the emulation code, it is probably there to protect against the old pseudo little endian implementations but doesn't make sense for real little endian. Signed-off-by:
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Anton Blanchard authored
The lppaca, slb_shadow and dtl_entry hypervisor structures are big endian, so we have to byte swap them in little endian builds. LE KVM hosts will also need to be fixed but for now add an #error to remind us. Signed-off-by:
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Anton Blanchard authored
Add endian annotation to various hypervisor structures which are defined as big endian. Signed-off-by:
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Alistair Popple authored
The device tree is big endian so make sure we byteswap on little endian. We assume any pHyp calls also return big endian results in memory. Signed-off-by:
Alistair Popple <alistair@popple.id.au> Signed-off-by:
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Alistair Popple authored
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Anton Blanchard authored
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Anton Blanchard authored
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Anton Blanchard authored
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Anton Blanchard authored
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Benjamin Herrenschmidt authored
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Anton Blanchard authored
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Anton Blanchard authored
We pass dma_window to of_parse_dma_window as a void * and then run through hoops to cast it back to a u32 array. In the process we lose endian annotation. Simplify it by just passing a __be32 * down. Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
Fix a couple of sparse warnings. Signed-off-by:
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Alistair Popple authored
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Anton Blanchard authored
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Anton Blanchard authored
RTAS expects arguments in the call buffer to be big endian so we need to byteswap on little endian builds Signed-off-by:
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Anton Blanchard authored
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Anton Blanchard authored
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Alistair Popple authored
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Ian Munsie authored
On PowerPC the device tree is always big endian, but the CPU could be either, so add be32_to_cpu where appropriate and change the types of device tree data to __be32 etc to allow sparse to locate endian issues. Signed-off-by:
Ian Munsie <imunsie@au1.ibm.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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Michael Neuling authored
When we have MMU on exceptions (POWER8) and a relocatable kernel, we need to branch from the initial exception vectors at 0x0 to up high where the kernel might be located. Currently we do this using the link register. Unfortunately this corrupts the link stack and instead we should use the count register. We did this for the syscall entry path in: 6a404806 powerpc: Avoid link stack corruption in MMU on syscall entry path but I stupidly forgot to do the same for other exceptions. This patch changes the initial exception vectors to use the count register instead of the link register when we need to branch up to the relocated kernel. I have a dodgy userspace test which loops calling a function that reads the PVR (mfpvr in userspace will be emulated by the kernel via the program check exception). On POWER8 and with CONFIG_RELOCATABLE=y, I get a ~10% performance improvement with my userspace test with this patch. Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Vasant Hegde authored
So far "/sys/devices/system/cpu/cpuX/topology/physical_package_id" was always default (-1) on ppc64 architecture. Now, some systems have an ibm,chip-id property in the cpu nodes in the device tree. On these systems, we now use this information to display physical_package_id. Signed-off-by:
Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by:
Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com> Signed-off-by:
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Mike Qiu authored
changes for V4: - changes the type of frozen_pe_no from %d to %llu in pr_devel() 'pe_no' hasn't been defined, it should be an typo error, it should be 'frozen_pe_no'. Also '__func__' has missed in IODA_EEH_DBG(), For safety reasons, use pr_devel() directly, instead of use IODA_EEH_DBG() Signed-off-by:
Mike Qiu <qiudayu@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
This reverts commit c8db32c8. The commit breaks the build of all my 64-bit embedded configs. It looks like gcc-4.7.3 doesn't know about e5500. Additionally it incorrectly does -mcpu=e5500 on a config that has both e5500 and A2 support enabled. Signed-off-by:
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Paul Mackerras authored
Some systems have an ibm,chip-id property in the cpu nodes in the device tree. On these systems, we now use that to compute the cpu_core_mask (i.e. the set of core siblings) rather than looking at cache properties. Signed-off-by:
Paul Mackerras <paulus@samba.org> Tested-by:
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Paul Mackerras authored
This factors out the details of updating cpu_core_mask into a separate function, to make it easier to change how the mask is calculated later. This makes no functional change. Signed-off-by:
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Paul Mackerras authored
The denormalized exception handler (denorm_exception_hv) has a couple of bugs. If the CONFIG_PPC_DENORMALISATION option is not selected, or the HSRR1_DENORM bit is not set in HSRR1, we don't test whether the interrupt occurred within a KVM guest. On the other hand, if the HSRR1_DENORM bit is set and CONFIG_PPC_DENORMALISATION is enabled, we corrupt the CFAR and PPR. To correct these problems, this replaces the open-coded version of EXCEPTION_PROLOG_1 that is there currently, and that is missing the saving of PPR and CFAR values to the PACA, with an instance of EXCEPTION_PROLOG_1. This adds an explicit KVMTEST after testing whether the exception is one we can handle, and adds code to restore the CFAR on exit. Signed-off-by:
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Mark Brown authored
This is another file we can generate so add it to the list. Signed-off-by:
Mark Brown <broonie@linaro.org> Signed-off-by:
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James Yang authored
Load/store indexed instructions where the index register RA=R0, such as "lfdx f1,0,r3", are not illegal. Load/store indexed with update instructions where the index register RA=R0, such as "lfdux f1,0,r3", are invalid, and, to be consistent with existing math-emu behavior for other invalid instruction forms, will signal as illegal. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
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Kevin Hao authored
Instead of implementing an empty giveup_fpu() function for each 32bit processor type, replace them with an unique empty inline function. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
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Kevin Hao authored
In the current kernel, the function flush_fp_to_thread() is not dependent on CONFIG_PPC_FPU. So most invocations of this function is not wrapped by CONFIG_PPC_FPU. Even through we don't really save the FPRs to the thread struct if CONFIG_PPC_FPU is not enabled, but there does have some runtime overhead such as the check for tsk->thread.regs and preempt disable and enable. It really make no sense to do that. So make it a nop when CONFIG_PPC_FPU is disabled. Also remove the wrapped #ifdef CONFIG_PPC_FPU when invoking this function. Signed-off-by:
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Kevin Hao authored
In commit c6e6771b(powerpc: Introduce VSX thread_struct and CONFIG_VSX) we add a invocation of flush_fp_to_thread() before copying the FPR or VSR to users. But we already invoke the flush_fp_to_thread() in this function. So remove one of them. Signed-off-by:
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