- 03 Aug, 2020 2 commits
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Stephen Boyd authored
- Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Make defines for bcm63xx-gate clks to use in DT - Support gate clks on BCM6318 SoCs - Add HDMI clks for BCM2711 SoCs - Support BCM2711 SoC firmware clks * clk-socfpga: clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK * clk-doc: clk: Clean up kernel-doc errors clk: <linux/clk-provider.h>: drop a duplicated word clk: add function documentation for clk_hw_round_rate() * clk-qcom: (38 commits) dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset clk: qcom: lpass: Add support for LPASS clock controller for SC7180 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180 clk: qcom: gdsc: Add support to enable retention of GSDCR clk: qcom: Export gdsc_gx_do_nothing_enable() to modules clk: qcom: Add graphics clock controller driver for SM8250 clk: qcom: Add graphics clock controller driver for SM8150 clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers dt-bindings: clock: add SM8250 QCOM Graphics clock bindings dt-bindings: clock: add SM8150 QCOM Graphics clock bindings dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc clk: qcom: gcc: remove unnecessary vco_table from SM8150 clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL clk: qcom: gcc: fix sm8150 GPU and NPU clocks dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax ... * clk-vc5: clk: vc5: use a dedicated struct to describe the output drivers dt-bindings: clk: versaclock5: convert to yaml MAINTAINERS: take over IDT VersaClock 5 clock driver dt-bindings: clk: versaclock5: fix 'idt' prefix typos clk: vc5: Add memory check to prevent oops clk: vc5: fix use of memory after it has been kfree'd clk: vc5: Enable addition output configurations of the Versaclock dt: Add additional option bindings for IDT VersaClock clk: vc5: Allow Versaclock driver to support multiple instances * clk-bcm: (44 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs dt-bindings: arm: bcm: Add a select to the RPI Firmware binding clk: bcm: dvp: Add missing module informations clk: bcm: rpi: Remove the quirks for the CPU clock clk: bcm2835: Don't cache the PLLB rate clk: bcm2835: Allow custom CCF flags for the PLLs Revert "clk: bcm2835: remove pllb" clk: bcm: rpi: Give firmware clocks a name clk: bcm: rpi: Discover the firmware clocks clk: bcm: rpi: Add an enum for the firmware clocks clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Use CCF boundaries instead of rolling our own clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Switch to clk_hw_register_clkdev ...
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Nicolas Saenz Julienne authored
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL feedback loop. Bypass it by zeroing fb_prediv_mask when running on bcm2711. Note that, since the prediv configuration bits were re-purposed, this was triggering miscalculations on all clocks hanging from the VPU clock, notably the aux UART, making its output unintelligible. Fixes: 42de9ad4 ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support") Reported-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.deTested-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 31 Jul, 2020 1 commit
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Douglas Anderson authored
The YAML schemas that landed forgot one clock: "bi_tcxo". Presumably the bindings were developed against the v4 version of the driver and when the ".name" was removed in v5 of the driver things broke. While touching this, add the needed includes in each example. I believe both examples are supposed to be independent of each other. Let's fix the bindings. Fixes: 381cc6f9 ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200731133006.1.Iee81b115f5be50d6d69500fe1bda11bba6e16143@changeidSigned-off-by:
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- 27 Jul, 2020 2 commits
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Konrad Dybcio authored
Add missing halt_check, hwcg_reg and hwcg_bit properties. These were likely omitted when porting the driver upstream. Signed-off-by:
Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com Fixes: f2a76a29 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by:
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Konrad Dybcio authored
This will be required in order to support the modem upstream. Signed-off-by:
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- 24 Jul, 2020 17 commits
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Taniya Das authored
The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Drop unused ret in probe function] Signed-off-by:
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Taniya Das authored
Add the GCC lpass clock which is required to access the LPASS core clocks. Signed-off-by:
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Taniya Das authored
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1595606878-2664-3-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Taniya Das authored
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by:
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Stephen Boyd authored
Two things aren't documented causing kernel-doc to fail when checking the core clk.c file. Fix them so that this file is clean. Signed-off-by:
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Stephen Boyd authored
A clk driver can be a module but the gdsc code is in the common module. Export this symbol so that allmodconfig builds keep working. Cc: Jonathan Marek <jonathan@marek.ca> Fixes: 0638226d ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers") Signed-off-by:
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Jonathan Marek authored
Add support for the graphics clock controller found on SM8250 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Tested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-12-jonathan@marek.caSigned-off-by:
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Jonathan Marek authored
Add support for the graphics clock controller found on SM8150 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by:
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Jonathan Marek authored
All gpucc drivers need this, so move it to common code instead of duplicating it in every gpucc driver. Signed-off-by:
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Jonathan Marek authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8250 SoCs. Signed-off-by:
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Jonathan Marek authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8150 SoCs. Signed-off-by:
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Jonathan Marek authored
These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 gpucc bindings. Signed-off-by:
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Jonathan Marek authored
The fixed alpha pll ops only use it for clamping in round_rate, which is unnecessary. This is consistent with SM8250 GCC not using vco_table. Signed-off-by:
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Jonathan Marek authored
Lucid PCAL_DONE is different from trion. Signed-off-by:
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Jonathan Marek authored
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by:
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Jonathan Marek authored
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL. Fixes: 548a9095 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Signed-off-by:
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Jonathan Marek authored
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it should be a 500us delay and not skip, however this matches what was done for other clocks that had 500us delay in downstream. Fixes: f73a4230 ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150") Signed-off-by:
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- 23 Jul, 2020 8 commits
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Luca Ceresoli authored
Reusing the generic struct vc5_hw_data for all blocks is handy. However it implies we allocate space the div_int and div_frc fields even for the output drivers where they are unused, and the clk_output_cfg0 and clk_output_cfg0_mask fields for all components even though they are used only for the output drivers. Use a dedicated struct for the output drivers so that each block uses exactly the fields it needs, not more. Signed-off-by:
Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20200723072603.1795-1-luca@lucaceresoli.netSigned-off-by:
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Luca Ceresoli authored
Convert to yaml the VersaClock bindings document. The mapping between clock specifier and physical pins cannot be described formally in yaml schema, then keep it verbatim in the description field. Signed-off-by:
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Luca Ceresoli authored
Marek has been the primary developer of this driver (thanks!). Now as he is not working on it anymore he suggested I take over maintainership. Cc: Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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Luca Ceresoli authored
'idt' is misspelled 'itd' in a few places, fix it. Fixes: 34662f6e ("dt: Add additional option bindings for IDT VersaClock") Signed-off-by:
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Maxime Ripard authored
The RaspberryPi firmware binding uses two compatible, include simple-bus. The select statement generated by default will thus select any node that has simple-bus, not all of them being the raspberrypi firmware node. This results in warnings being wrongfully reported. Let's add a custom select statement to fix that. Fixes: d4c708c0 ("dt-bindings: arm: bcm: Convert BCM2835 firmware binding to YAML") Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200626115433.125735-1-maxime@cerno.techAcked-by:
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Adam Ford authored
When getting the names of the child nodes, kasprintf is used to allocate memory which is used to create the string for the node name. Unfortunately, there is no memory check to determine if this allocation fails, it may cause an error when trying to get child node name. This patch will check if the memory allocation fails, and returns and -ENOMEM error instead of blindly moving on. Fixes: 260249f9 ("clk: vc5: Enable addition output configurations of the Versaclock") Suggested-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Adam Ford <aford173@gmail.com> Reviewed-by:
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Colin Ian King authored
There are a several places where printing an error message of init.name occurs after init.name has been kfree'd. Also the failure message is duplicated each time in the code. Fix this by adding a registration error failure path for these cases, moving the duplicated error messages to one common point and kfree'ing init.name only after it has been used. Changes also shrink the object code size by 171 bytes (x86-64, gcc 9.3): Before: text data bss dec hex filename 21057 3960 64 25081 61f9 drivers/clk/clk-versaclock5.o After: text data bss dec hex filename 20886 3960 64 24910 614e drivers/clk/clk-versaclock5.o Addresses-Coverity: ("Use after free") Fixes: f491276a ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200625132736.88832-1-colin.king@canonical.comReviewed-by:
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Loic Poulain authored
Fix errors reported by dt_binding_check. - Fix literal block scalar for dts example - Fix schema identifier URI Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1595326714-20485-1-git-send-email-loic.poulain@linaro.orgReviewed-by:
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- 21 Jul, 2020 4 commits
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Taniya Das authored
The display gpll0 branch clock inside GCC needs to always be enabled. Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk controller (dispcc) will stop clocking while sourcing from gpll0 when this branch inside GCC is turned off during unused clk disabling. We can never turn this branch off because the AHB clk for the display subsystem is needed to read/write any registers inside the display subsystem including clk related ones. This makes this branch a really easy way to turn off AHB access to the display subsystem and cause all sorts of mayhem. Let's just make the clk ops keep the clk enabled forever and ignore any attempts to disable this clk so that dispcc accesses keep working. Signed-off-by:
Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") [sboyd@kernel.org: Fill out commit text more] Signed-off-by:
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Ansuel Smith authored
Add support for child probing needed for tsens driver that share the same regs of gcc for this platform. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by:
Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/20200716022817.30439-2-ansuelsmth@gmail.comSigned-off-by:
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Wei Yongjun authored
The sparse tool complains as follows: drivers/clk/qcom/clk-cpu-8996.c:341:19: warning: symbol 'cpu_msm8996_clks' was not declared. Should it be static? This variable is not used outside of clk-cpu-8996.c, so this commit marks it static. Fixes: 03e342dc ("clk: qcom: Add CPU clock driver for msm8996") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200714142155.35085-1-weiyongjun1@huawei.comSigned-off-by:
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Sivaprakash Murugesan authored
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org Fixes: e7fb524c ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe") Signed-off-by:
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- 20 Jul, 2020 1 commit
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Randy Dunlap authored
Drop the repeated word "not" in a comment. Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20200719002830.20319-1-rdunlap@infradead.orgSigned-off-by:
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- 11 Jul, 2020 5 commits
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Konrad Dybcio authored
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by:
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Sivaprakash Murugesan authored
Add missing clocks and resets for pcie port0 of ipq8074 devices. Co-developed-by:
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by:
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Sivaprakash Murugesan authored
Add missing clock bindings for PCIe port0 of ipq8074. Co-developed-by:
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Loic Poulain authored
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. Signed-off-by:Rajendra Nayak <rnayak@codeaurora.org> Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84Signed-off-by:
Ilia Lin <ilialin@codeaurora.org> Ilia Lin: - reworked clock registering - Added clock-tree diagram - non-builtin support - clock notifier on rate change - https://lkml.org/lkml/2018/5/24/123Signed-off-by:
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Ilia Lin authored
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. Signed-off-by:
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