- 05 Jul, 2013 1 commit
-
-
Alex Deucher authored
Fix patching of vddc values for SI and enable manually forcing clocks to default levels as per NI. This improves the out of the box performance with SI asics. Signed-off-by:Alex Deucher <alexander.deucher@amd.com>
-
- 03 Jul, 2013 5 commits
-
-
Alex Deucher authored
Some asic revisions need to disable PG when UVD is active. Signed-off-by: -
Alex Deucher authored
Causes hangs for some people. Signed-off-by: -
Alex Deucher authored
Causes hangs for some people. Signed-off-by: -
Alex Deucher authored
They cause problems with dynamic clocking. Signed-off-by: -
Alex Deucher authored
Signed-off-by:
-
- 02 Jul, 2013 2 commits
-
-
Mike Lothian authored
Add #include <linux/seq_file.h> to *_dpm.c files Signed-off-by: -
Alex Deucher authored
For chips without debugfs dpm support say that it's not implemented rather than not supported to avoid confusion about DPM support in general. Signed-off-by:
-
- 01 Jul, 2013 32 commits
-
-
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: -
Alex Deucher authored
This lays the frameworks to report realtime power level feedback. Signed-off-by: -
Alex Deucher authored
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: -
Alex Deucher authored
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: -
Alex Deucher authored
Bad pointer math. Fixes hangs in state transitions with BTC+ asics. Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
Function doesn't do anything useful. Signed-off-by: -
Dave Airlie authored
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Various fixes that make surviving concurrent piglit more possible. - Buffer object deletion no longer synchronous - Context/register initialisation updates that have been reported to solve some stability issues (particularly on some problematic GF119 chips) - Kernel side support for VP2 video decoding engines * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits) drm/nvd0-/disp: handle case where display engine is missing/disabled drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 drm/nouveau/bsp/nv84: initial vp2 engine implementation drm/nouveau/vp/nv84: initial vp2 engine implementation drm/nouveau/core: xtensa engine base class implementation drm/nouveau/vdec: fork vp3 implementations from vp2 drm/nouveau/core: move falcon class to engine/ drm/nouveau/kms: don't fail if there's no dcb table entries drm/nouveau: remove limit on gart drm/nouveau/vm: perform a bar flush when flushing vm drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches drm/nvc8/gr: update initial register/context values drm/nvc4/gr: update initial register/context values drm/nvc1/gr: update initial register/context values drm/nvc3/gr: update initial register/context values drm/nvc0/gr: update initial register/context values drm/nvd9/gr: update initial register/context values drm/nve4/gr: update initial register/context values drm/nvc0-/gr: bump maximum gpc/tpc limits drm/nvf0/gr: initial register/context setup ...
-
Maarten Lankhorst authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
-
Ben Skeggs authored
No code changes, proven by envyas producing identical binaries. Signed-off-by: -
Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
-
Ilia Mirkin authored
Signed-off-by:
-
Ilia Mirkin authored
Signed-off-by:
-
Ilia Mirkin authored
Signed-off-by:
-
Ben Skeggs authored
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: -
Ben Skeggs authored
Fixes module not loading on Tesla K20. Signed-off-by: -
Maarten Lankhorst authored
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by:
Maarten >Lnkhorst <maarten.lankhorst@canonical.com> Signed-off-by:
-
Maarten Lankhorst authored
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by:
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by:
-
