- 08 Jul, 2013 2 commits
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Maarten Lankhorst authored
"drm/nve0-/gr: some new gpc registers can have multiple copies" 5ee86c41 caused a regression for nvc0, because the bit indicating last transfer has occured was no longer set, resulting in random system lockups. Reported-by:
Ronald Uitermark <ronald645@gmail.com> Tested-by:
Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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- 05 Jul, 2013 22 commits
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Ilia Mirkin authored
This is the nva3 counterpart to commit beba44b1 (drm/nv84/disp: Fix HDMI audio regression). The regression happened as a result of refactoring in commit 8e9e3d2d (drm/nv84/disp: move hdmi control into core). Reported-and-tested-by:
Max Baldwin <archerseven@gmail.com> Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Emil Velikov authored
The commit commit 476e84e1 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon Feb 11 09:24:23 2013 +1000 drm/nv50-/disp: initial supervisor support for off-chip encoders changed the write mask in one of the interrupt functions for on-chip encoders, causing a regression in certain VGA dual-head setups. This commit reintroduces the mask thus resolving the regression Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129Reported-and-Tested-by:
Yves-Alexis <corsac@debian.org> Cc: stable@vger.kernel.org [3.9+] CC: Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by:
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Marcin Slusarz authored
Page tables on nv50 take 48kB, which can be hard to allocate in one piece. Let's use vmalloc. Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Cc: stable@vger.kernel.org [3.7+] Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
NVC1/NVD9 are the only chipsets that should have anything different happen on them after this. We previously weren't doing these register modifications, and NVIDIA do. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This can be generalised and used on GK104 (probably even GF117), but lets just make it work for now. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Maarten Lankhorst authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Generated context verified to be the same for all supported chipsets. Signed-off-by:
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- 01 Jul, 2013 16 commits
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Maarten Lankhorst authored
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Ben Skeggs authored
No code changes, proven by envyas producing identical binaries. Signed-off-by: -
Ilia Mirkin authored
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Ilia Mirkin authored
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Ilia Mirkin authored
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Ilia Mirkin authored
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Ben Skeggs authored
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: -
Ben Skeggs authored
Fixes module not loading on Tesla K20. Signed-off-by: -
Maarten Lankhorst authored
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by:
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Maarten Lankhorst authored
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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