- 07 Jun, 2021 11 commits
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Christophe JAILLET authored
s/than/then/ Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiapeng Chong authored
Clean up the following includecheck warning: ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: dce110_hw_sequencer.h is included more than once. No functional change. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Bernard Zhao authored
remove no need variable, just return the DC_OK Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Eric Huang authored
Add the parameter table_freed description on function description. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Wan Jiabing authored
kfd_svm.h is included duplicately in commit 42de677f ("drm/amdkfd: register svm range"). After checking possible related header files, remove the former one to make the code format more reasonable. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
For GTT allocations with a GART address the res contains the VMID0 addresses and can't be used for VM handling. So ignore the res when the pages array is given or we fill the page tables with nonsense. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Peng Ju Zhou authored
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so NULL pointer must be checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check. Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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John Clements authored
Disable support on APU Reviewed-by:
Changfeng <Changfeng.Zhu@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Hawking Zhang authored
Follow the same apporach as GFX to handle SDMA poison consumption. Send SIGBUS to application when receives SDMA_ECC interrupt and issue gpu reset either mode 2 or mode 1 to get the engine back Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<dennis.li@amd.com> Signed-off-by:
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Philip Yang authored
prange->offset is for VRAM range mm_nodes, if multiple ranges share same mm_nodes, migrate range back to VRAM will reuse the VRAM at offset of the same mm_nodes. For system memory pages_addr array, the offset is always 0, otherwise, update GPU mapping will use incorrect system memory page, and cause system memory corruption. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Rohit Khaire authored
In SRIOV environment, KMD should access SDMA registers through RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when the flag is enabled. Signed-off-by:
Rohit Khaire <rohit.khaire@amd.com> Reviewed-by:
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- 04 Jun, 2021 29 commits
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Alex Deucher authored
Missing proper DC_FP_START/DC_FP_END. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Alex Deucher authored
Port the necessary changes from previous DCN versions. Reviewed-by:
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Nicholas Kazlauskas authored
To enable output on real display instead of virtual. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
To enable compiling and using DCN3.1 ASICs with physical output. Acked-by:
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Nicholas Kazlauskas authored
To detect DCN3.1 ASICs and to enable the appropriate number of CRTCs, pick the right validation paths for display formats and to use the right DC interfaces. Acked-by:
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Nicholas Kazlauskas authored
Preparation for compiling DCN3.1 support. Acked-by:
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Nicholas Kazlauskas authored
Container for hardware resources and blocks for DCN3.1, also adds new DC debug flags used with DCN3.1. Acked-by:
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Nicholas Kazlauskas authored
DMCUB has a deferred z10 restore process that needs signalling from driver to occur. This needs to be done on any interface that programs the hardware state or sequences where we expect to have the same hardware state as before. Acked-by:
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Nicholas Kazlauskas authored
Add DCN3.1 specific hardware sequence programming - extending off of our existing DCN3/DCN2 support. Extend stream hardware sequencing to include new DCCG programming. Acked-by:
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Nicholas Kazlauskas authored
Updated interfaces for multiple eDP backlight caps. Added support for interpreting the new BIOS command tables on DCN3.1. Acked-by:
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Nicholas Kazlauskas authored
New DTM interface is V3 and we need to extend our existing support to enable HDCP on DCN3.1. Version the helpers and fallback to the older versions on failure in the new interfaces. Acked-by:
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Nicholas Kazlauskas authored
The PANEL block handles embedded panel power and backlight programming. This programming and sequencing is now owned by DMCUB and driver will call into the interface for backlight status and programming. Acked-by:
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Nicholas Kazlauskas authored
DMCU-B (Display Micro-Controller Unit B) is a display microcontroller used for shared display functionality with BIOS and for advanced power saving display features. Extends the command header to include new DCN3.1 functionality. Adds new interfaces to DC dmub interface as well for z-state support. Acked-by:
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Nicholas Kazlauskas authored
Extends off of DCN3. Acked-by:
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Nicholas Kazlauskas authored
Add IRQ services for DCN3.1 to handle hardware generated interrupts. Acked-by:
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Nicholas Kazlauskas authored
DML (Display mode library) is used for calculating watermarks, bandwidth and for validating display configurations. Acked-by:
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Nicholas Kazlauskas authored
Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared hardware sequencer helpers to use these hooks. HW Blocks: +--------++------+ +----------+ |DCHUBBUB|| HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | <---------> | DWB | +--------+ +--------+ | ^ v | +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ No changes to MMHUBBUB or DWB programming, added to diagram for clarity. Acked-by: -
Nicholas Kazlauskas authored
Add support for programming the DCN3.1 OPTC (Output Timing Controller) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ There are no changes to OPP or MPC for DCN3.1, so the diagram will include them in this patch. Acked-by: -
Nicholas Kazlauskas authored
Add support for the DIO (Display IO) block of DCN3.1 which controls legacy HDMI/DP stream/link encoding. HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Includes some updates to core logic for link encoder assignment and future support for new high bandwidth output. v2: squash in unused variable fix (Alex) Acked-by: -
Nicholas Kazlauskas authored
Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ | DCCG | +--------+ Acked-by: -
Nicholas Kazlauskas authored
Adds support for clock requests for the various parts of the DCN3.1 IP and the interfaces and definitions for sending messages to SMU/PMFW. Includes new support for z9/10, detecting SMU timeout and p-state support enablement. Acked-by:
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Nicholas Kazlauskas authored
[Why & How] To determine whether the chip is yellow carp or not and which revision it is. Acked-by:
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Nicholas Kazlauskas authored
[Why & How] We'll need these in driver for phy tuning in DCN3.1. Multiple eDP support also requires understanding which LCD the backlight curve in atombios is for. Acked-by:
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James Zhu authored
Add video_codecs query support for yellow carp. Acked-by:
James Zhu <James.Zhu@amd.com> Acked-by:
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Xiaomeng Hou authored
PMFW provides specific messages for setting fclk freq range thus adjust the power level. There's misusing of these messages when setting dpm mclk. Since actually mclk could adjust automatically complying with fclk, remove standalone support for mclk dpm level setting. Acked-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Aaron Liu authored
This patch adds mode2 reset support for yellow carp. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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Xiaomeng Hou authored
This patch enables editing sysfs file power_dpm_force_performance_level for yellow carp. User could thus adjust the dpm forced level. v2: enable fine grain control of GFXCLK only when in manual performance level mode. In other mode, the min/max range of GFXCLK will be reset to corresponding values. Ex: To enable min 300MHz / max 600MHz gfx clocks 1) echo manual > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 0 300 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo s 1 600 > /sys/bus/pci/devices/.../pp_od_clk_voltage 4) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Signed-off-by:
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Xiaomeng Hou authored
Skip disabled sa to correct the cu_info and active_rbs for yellow carp. Signed-off-by:
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Xiaomeng Hou authored
Register callback in gfxhub functions to program the bypass groups in gc_utcl2 corresponding to harvested SA. v2: update comments (Alex) Signed-off-by:
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